- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369659 > CDRM622 (Lineage Power) 622 Mbits/s Multichannel Digital Timing Recovery(622M位/秒 多通道數(shù)字定時恢復) PDF資料下載
參數(shù)資料
| 型號： | CDRM622 |
| 廠商： | Lineage Power |
| 英文描述： | 622 Mbits/s Multichannel Digital Timing Recovery(622M位/秒 多通道數(shù)字定時恢復) |
| 中文描述： | 622 Mbits /秒多通道數(shù)字定時恢復（622M位/秒多通道數(shù)字定時恢復） |
| 文件頁數(shù)： | 6/14頁 |
| 文件大?。?/td> | 278K |
| 代理商： | CDRM622 |
CDRM622
622 Mbits/s Multichannel Digital Timing Recovery Macrocell
Data Sheet
June 1999
6
Lucent Technologies Inc.
Simulation Interface
PLL Bypass
Device simulating, debugging, and testing with a working PLL is not recommended. Therefore, a test mode that
bypasses the PLL is provided. Functional simulation and factory testing can make use of this mode. The logic of
the data paths remain functional. Only the 622.08 MHz clock source is changed to the test clock. For factory test-
ing, the PLL is separately exercised and monitored through the test port. Figure 3 illustrates this mode.
Logical Timing
Figure 4 and Figure 5 illustrate the functional timing relationships during PLL bypass mode operation.
Internal Clock Synchronization
When the PLL is bypassed, the internal clock dividers are not automatically aligned with the phase of the input ref-
erence clock. Resets are provided as an aid to force a relationship. During PLL bypass, the clock dividers are
clocked by the test clock. The first falling edge of the test clock after the resets become inactive will generate a ris-
ing edge of the internal 77.76 MHz clocks. PLL bypass simulation test benches should be designed so that the
device input signals driving TSTCLK, REF78, RESETRN, and RESETTN are sequenced to closely align the inter-
nal clocks with the reference clock. Figure 6 illustrates this sequence.
Table 2. Simulation Signals
Signal Name
Type
Description
BYPASS
I
(Active-High).
Enables functional bypassing of the 622 MHz clock synthesis with
TSTCLK. Receiver and transmitter pass data in a logically correct manner based on
the test clock timing.
TSTCLK
I
Test clock for emulation of 622.08 MHz clock during PLL bypass. This input can run
up to 155 MHz for factory testing. Also used for low-speed fault coverage testing.
RESETTN
I
(Active-Low).
Resets transmitter clock division counter to enable synchronizing the
internal 77.76 MHz clock to the reference clock during PLL bypass.
RESETRN
I
(Active-Low).
Resets receiver clock division counter to enable synchronizing the
recovered 77.76 MHz clocks to the reference clock during PLL bypass.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDT13003B | NPN SILICON POWER TRANSISTOR |
| CDT13003 | NPN SILICON POWER TRANSISTOR |
| CDT13003A | NPN SILICON POWER TRANSISTOR |
| CDT13003C | NPN SILICON POWER TRANSISTOR |
| CDT13003E | NPN SILICON POWER TRANSISTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDRMILPRF55681 | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:Surface Mount Multilayer Ceramic Chip Capacitors MIL Qualified, Type CDR |
| CDR-MIL-PRF-55681 | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:Surface Mount Multilayer Ceramic Chip Capacitors Qualified, Type CDR |
| CD-ROM | 制造商:Allegro MicroSystems 功能描述:CD-ROM ALLEGRO DATA |
| CD-ROM.REV03 | 制造商:Maxim Integrated Products 功能描述:CD-ROM MAXIM DATA |
| CDROM/ACCESSORY | 制造商:Teac 功能描述:ACCESS KIT FOR TEAC CDROM |
發(fā)布緊急采購，3分鐘左右您將得到回復。