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參數(shù)資料
| 型號： | CDB4382A |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 22/50頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR CS4382A DAC |
| 標準包裝： | 1 |
| DAC 的數(shù)量： | 8 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 192k |
| 數(shù)據(jù)接口： | 串行 |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | CS4382A |
| 產(chǎn)品目錄頁面： | 757 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | CS4382A-DQZR-ND - IC DAC 8CH 114DB 192KHZ 48-LQFP CS4382A-DQZ-ND - IC DAC 8CH 114DB 192KHZ 48-LQFP CS4382A-CQZR-ND - IC DAC 8CH 114DB 192KHZ 48-LQFP 598-1061-ND - IC DAC 8CH 114DB 192KHZ 48LQFP |
| 其它名稱： | 598-1524 |
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DS618F2
29
CS4382A
4.13
Recommended Procedure for Switching Operational Modes
For systems where the absolute minimum in clicks and pops is required, it is recommended that the MUTE
bits are set prior to changing significant DAC functions (such as changing sample rates or clock sources).
The mute bits may then be released after clocks have settled and the proper modes have been set.
It is required to have the device held in reset if the minimum high/low time specs of MCLK cannot be met
during clock source changes.
4.14
Control Port Interface
The Control Port is used to load all the internal register settings in order to operate in Software Mode (see
the “Filter Plots” on page 42). The operation of the Control Port may be completely asynchronous with the
audio sample rate. However, to avoid potential interference problems, the Control Port pins should remain
static if no operation is required.
The Control Port operates in one of two modes: IC or SPI.
4.14.1
MAP Auto Increment
The device has MAP (memory address pointer) auto-increment capability enabled by the INCR bit (also
the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive IC writes or reads and
SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or
writes of successive registers.
4.14.2
IC Mode
In the IC Mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial
Control Port clock, SCL (see Figure 18 for the clock to data relationship). There is no CS pin. Pin AD0
enables the user to alter the chip address (001100[AD0][R/W]) and should be tied to VLC or GND, as re-
quired, before powering up the device. If the device ever detects a high-to-low transition on the AD0/CS
pin after power-up, SPI Mode will be selected.
4.14.2.1 IC Write
To write to the device, follow the procedure below while adhering to the Control Port Switching Specifica-
tions in Section 2.
1. Initiate a START condition to the IC bus followed by the address byte. The upper 6 bits must be
001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth
bit of the address byte is the R/W bit.
2. Wait for an acknowledge (ACK) from the part; then write to the memory address pointer, MAP. This
byte points to the register to be written.
3. Wait for an acknowledge (ACK) from the part; then write the desired data to the register pointed to by
the MAP.
4. If the INCR bit (see Section 4.14.1) is set to 1, repeat the previous step until all the desired registers
are written, then initiate a STOP condition to the bus.
5. If the INCR bit is set to 0 and further IC writes to other registers are desired, it is necessary to initiate
a repeated START condition and follow the procedure detailed from step 1. If no further writes to other
registers are desired, initiate a STOP condition to the bus.
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