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參數(shù)資料
| 型號(hào)： | CD4510BKMSR |
| 廠商： | INTERSIL CORP |
| 元件分類： | 計(jì)數(shù)器 |
| 英文描述： | 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, CDFP16 |
| 封裝： | CERAMIC, DFP-16 |
| 文件頁(yè)數(shù)： | 3/11頁(yè) |
| 文件大?。?/td> | 141K |
| 代理商： | CD4510BKMSR |
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All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certication.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Ofce Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
FIGURE 15. CASCADING COUNTER PACKAGES
* CARRY OUT lines at the 2nd, 3rd, etc., stages may have a negative-going glitch pulse resulting from differential delays of different CD4010/16BMS
IC’S. These negative going glitches do not affect proper CD4029BMS operation. However, if the CARRY OUT signals are used to trigger other edge-
sensitive logic devices, such as FF’S or counters, the CARRY OUT signals should be gated with the clock signal using a 2-input OR gate such as
CD4071BMS.
UP/D
R
PE
CL Q1 Q2 Q3 Q4
CI
CO
J1 J2 J3 J4
CD4510/16BMS
UP/D
R
PE
CL Q1 Q2 Q3 Q4
CI
CO
J1 J2 J3 J4
UP/D
R
PE
CL Q1 Q2 Q3 Q4
CI
CO
J1 J2 J3 J4
*
UP/DOWN
PRESET
ENABLE
CLOCK
RESET
PARALLEL CLOCKING
CD4510/16BMS
Ripple Clocking Mode: The up/down control can be changed at any count. The only restriction on changing the up/down control is that the
clock input to the rst counting stage must be high. For cascading counters operating in a xed up-count or down-count mode, the OR gates
are not required between stages, and CO is connected directly to the CL input of the next stage with CI grounded.
UP/D
R
PE
CL Q1 Q2 Q3 Q4
CI
CO
J1 J2 J3 J4
UP/D
R
PE
CL Q1 Q2 Q3 Q4
CI
CO
J1 J2 J3 J4
UP/D
R
PE
CL Q1 Q2 Q3 Q4
CI
CO
J1 J2 J3 J4
UP/DOWN
PRESET
ENABLE
CLOCK
RESET
1/4 CD4071B
RIPPLE CLOCKING
CD4510/16BMS
CD4510BMS, CD4516BMS
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