參數(shù)資料
型號(hào)： CD4510BKMSR
廠商： INTERSIL CORP
元件分類(lèi)： 計(jì)數(shù)器
英文描述： 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, CDFP16
封裝： CERAMIC, DFP-16
文件頁(yè)數(shù)： 11/11頁(yè)
文件大?。?/td> 141K
代理商： CD4510BKMSR
9
FIGURE 9. TYPICAL MAXIMUM CLOCK INPUT FREQUENCY vs
SUPPLY VOLTAGE
FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION vs
FREQUENCY
Typical Performance Characteristics (Continued)
0
5
SUPPLY VOLTAGE (VDD)
AMBIENT TEMPERATURE (TA) = +25
oC
LOAD CAPACITANCE (CL) = 50pF
10
15
MAXIMUM
CLOCK
INPUT
FREQ
UENCY
(fCL
MAX)
(MHz)
510
15
20
10V
5V
10V
8
6
4
2
8
6
4
2
104
103
10
PO
WER
DISSIP
A
TION
PER
GA
TE
(PD)
(
W)
SUPPLY VOLTS (VDD) = 15V
AMBIENT TEMPERATURE (TA)
tr, tf = 20ns
= +25oC
8
6
4
2
102
8
6
4
2
INPUT FREQUENCY (fCL) (kHz)
01
1
8
6
4
2
10
8
6
4
2
102
8
6
4
2
103
8
6
4
2
104
CL = 15pF
CL = 50pF
Test Circuit and Waveform
FIGURE 11. POWER DISSIPATION TEST CIRCUIT AND INPUT WAVEFORM
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
CL
100
F
ID
500
F
PULSE
GENERATOR
50%
10%
90%
20ns
VDD
20ns
VARIABLE
WIDTH
VSS
Acquisition System
FIGURE 12. TYPICAL 16 CHANNEL, 10 BIT DATA ACQUISITION SYSTEM
16 CHANNEL
MULTIPLEXER
CD4067
SELECT
INPUTS
SAMPLE
AND
HOLD
10 BIT
A/D
CONVERTER
CONVERSION
LOGIC
Q1
Q4
CD4516BMS
AMPLI-
FIER
CLOCK
PRESET ENABLE
END
CLOCK
START
ANALOG
DATA
INPUTS
PARALLEL
DATA
OUTPUTS
PRESET
INPUTS
NOTE:
This acquisition system can be operated in the random access mode by
jamming in the channel number at the present inputs, or in the sequential
mode by clocking the CD4516BMS.
CD4510BMS, CD4516BMS
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