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參數(shù)資料
| 型號： | CD4027BC |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Dual J-K Master/Slave Flip-Flop with Set and Reset(帶置位和復(fù)位的雙J-K主從觸發(fā)器) |
| 中文描述： | 雙JK主/從觸發(fā)器的設(shè)置和復(fù)位（帶置位和復(fù)位的雙JK主從觸發(fā)器） |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 58K |
| 代理商： | CD4027BC |
October 1987
Revised January 1999
C
1999 Fairchild Semiconductor Corporation
DS005958.prf
www.fairchildsemi.com
CD4027BC
Dual J-K Master/Slave Flip-Flop with Set and Reset
General Description
The CD4027BC dual J-K flip-flops are monolithic comple-
mentary MOS (CMOS) integrated circuits constructed with
N- and P-channel enhancement mode transistors. Each
flip-flop has independent J, K, set, reset, and clock inputs
and buffered Q and Q outputs. These flip-flops are edge
sensitive to the clock input and change state on the posi-
tive-going transition of the clock pulses. Set or reset is
independent of the clock and is accomplished by a high
level on the respective input.
All inputs are protected against damage due to static dis-
charge by diode clamps to V
DD
and V
SS
.
Features
I
Wide supply voltage range:
I
High noise immunity:
3.0V to 15V
0.45 V
DD
(typ.)
Fan out of 2 driving 74L
I
Low power TTL compatibility:
or 1 driving 74LS
I
Low power:
I
Medium speed operation:
supply
50 nW (typ.)
12 MHz (typ.) with 10V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Top View
Truth Table
I
=
HIGH Level
O
=
LOW Level
X
=
Don't Care
=
LOW-to-HIGH
=
HIGH-to-LOW
Note 1:
t
n
1
refers to the time interval prior to the positive clock pulse
transition
Note 2:
t
n
refers to the time intervals after the positive clock pulse
transition
Note 3:
Level Change
Order Number
CD4027BCM
CD4027BCN
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Inputs t
n
1
(Note 1)
Outputs t
n
(Note 2)
CL
(Note 3)
J
K
S
R
Q
Q
Q
I
X
O
X
I
X
X
X
X
O
O
O
O
O
I
O
I
O
O
O
O
O
O
I
I
O
I
O
I
X
X
X
X
I
I
O
O
I
I
X
O
X
X
X
X
X
O
O
(No Change)
O
I
I
X
X
X
I
O
I
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD4027BCM | 功能描述:觸發(fā)器 Dual J-K Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| CD4027BCMX | 功能描述:觸發(fā)器 Dual J-K Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| CD4027BCN | 功能描述:觸發(fā)器 Dual J-K Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| CD4027BD | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CD4027BD/3 | 制造商:RCA 功能描述:Flip Flop, Dual, J/K Type, 16 Pin, Ceramic, DIP |
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