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參數(shù)資料
| 型號(hào)： | CD4027BMS |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS Dual J-K Master-Slave Flip-Flop(CMOS雙 J-K主從觸發(fā)器) |
| 中文描述： | CMOS雙JK主從觸發(fā)器（的CMOS雙JK主從觸發(fā)器） |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 72K |
| 代理商： | CD4027BMS |
7-780
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
CD4027BMS
CMOS Dual J-K
Master-Slave Flip-Flop
Pinout
CD4027BMS
TOP VIEW
Functional Diagram
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
Q2
Q2
CLOCK 2
RESET 2
K2
J2
VSS
SET 2
VDD
Q1
CLOCK 1
RESET 1
K1
J1
SET 1
Q1
VSS
VDD
16
8
RESET 2
Q1
RESET1
SET2
Q2
5
Q2
10
11
13
12
7
1
K2
2
Q1
SET 1
9
4
15
14
6
3
J2
CLOCK2
J1
K1
CLOCK1
F/F1
F/F2
Features
High Voltage Type (20V Rating)
Set - Reset Capability
Static Flip-Flop Operation - Retains State Indefinitely
with Clock Level Either “High” or “Low”
Medium Speed Operation - 16MHz (typ.) Clock Toggle
Rate at 10V
Standardized Symmetrical Output Characteristics
100% Tested For Quiescent Current at 20V
Maximum Input Current of 1
μ
A at 18V Over Full
Package-Temperature Range;
- 100nA at 18V and +25
o
C
Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
5V, 10V and 15V Parametric Ratings
Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
Registers, Counters, Control Circuits
Description
CD4027BMS is a single monolithic chip integrated circuit con-
taining two identical complementary-symmetry J-K master-
slave flip-flops. Each flip-flop has provisions for individual J, K,
Set Reset, and Clock input signals. Buffered Q and Q signals
are provided as outputs. This input-output arrangement pro-
vides for compatible operation with the Intersil CD4013B dual D
type flip-flop.
The CD4027BMS is useful in performing control, register, and
toggle functions. Logic levels present at the J and K inputs
along with internal self-steering control the state of each flip-
flop; changes in the flip-flop state are synchronous with the pos-
itive-going transition of the clock pulse. Set and reset functions
are independent of the clock and are initiated when a high level
signal is present at either the Set or Reset input.
The CD4027BMS is supplied in these 16-lead outline pack-
ages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack H6W
H4T
H1E
December 1992
File Number
3302
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD4027BMT | 功能描述:觸發(fā)器 CMOS Dual J-K Master Slave RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| CD4027BMTE4 | 功能描述:觸發(fā)器 CMOS Dual J-K Master Slave RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| CD4027BMTG4 | 功能描述:觸發(fā)器 CMOS Dual J-K Master Slave RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| CD4027BNS | 制造商:Texas Instruments 功能描述: |
| CD4027BNSR | 功能描述:觸發(fā)器 Dual Master/Slave RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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