參數(shù)資料
型號(hào)： CCU3000-I
廠商： MICRONAS SEMICONDUCTOR HOLDING AG
元件分類： 微控制器/微處理器
英文描述： Central Control Unit
中文描述： MICROCONTROLLER, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 14/77頁(yè)
文件大?。?/td> 837K
代理商： CCU3000-I
CCU 3000, CCU 3000-I
CCU 3001, CCU 3001-I
MICRONAS INTERMETALL
14
2.13. Multifunctional Timer
The multifunctional timer for the CCU 3000, CCU 3001
has quite an unusual structure. It can serve as:
– event counter
– frequency counter
– pulse-length meter
– timer
– rate multiplier
– PWM
– asynchronous, serial interface
Each timer has a reserved pin and an interrupt. The pin
is either input or output, depending on its function. Used
as an output it has a push-pull structure. The timer con-
sists of three main parts:
– start and stop detector
– internal time reference
– accumulator and arithmetic unit
The start and stop detector controls the internal pulse
generator to synchronize counter and meter operations.
The timer itself does not consist of a counter circuit, but
of an accumulator and an adder. This configuration
works as a counter with adjustable step length, as a shift
register, as a PWM and as a rate multiplier. Change-over
of operation modes can easily be effected.
Each of the multifunctional timer circuits of the CCU is
realized as two 8-bit accumulators. In addition, there is
a separate adder register for each of them. Both the ac-
cumulator and the adder may be accessed by the CPU
via data bus. The accumulator has a shadow register the
CPU may write to and the adder bus register may be
read and written to.
While the adder register forms one side of the adder, the
other side is either the output of the adder or the content
of the accu shadow register. With every accu clock pulse
either of these bytes is used. If no “LOAD” signal is ac-
tive, the adder output is used. With “LOAD” active, the
following accu clock pulse uses the content of the accu
shadow register as adder input. The “LOAD” signal is
derived from 1 out of 4 sources, selectable with bits 3
and 4 of control byte 3. Accu clock is selectable with bits
1 and 2 in control byte 2. Instead of the content of the ad-
der register, accessible by the CPU, a hard-wired ‘-1’
may be used as input of the other side of the adder (bits
1 and 2 in control byte 3). By adding ‘-1’ to the accu’s
content, the adder works as a standard down counter.
With specific “READ LATCH” signals (control byte 2, bits
3, 4 and 5) and using the adder register as adder input,
its content defines the step width of the counter.
In addition to its parallel byte connections, the adder reg-
isters have serial inputs and outputs. A serial clock shifts
its contents. To hit the middle of serial data, the timer’s
prescaler has a half load feature, controlled with bit 1 in
control byte 1.
Fig. 2–14
shows a detailed diagram of the high part of
the reloadable accumulator and its adder register. For
examples of timer applications please refer to “Applica-
tion Note CCU 3000/3001 Timers”.
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