參數(shù)資料
型號: CBTU4411EE
廠商: NXP Semiconductors N.V.
元件分類: 開關(guān)
英文描述: 11-bit DDR2 SDRAM MUX-bus switch with 12 Ohm ON resistance
封裝: CBTU4411EE<SOT856-1 (LFBGA72)|<<http://www.nxp.com/packages/SOT856-1.html<1<Always Pb-free,;CBTU4411EE<SOT856-1 (LFBGA72)|<<http://www.nxp.com/packages/SOT856-1.html<1
文件頁數(shù): 16/20頁
文件大小: 107K
代理商: CBTU4411EE
CBTU4411_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 12 October 2009
5 of 20
NXP Semiconductors
CBTU4411
11-bit DDR2 SDRAM MUX/bus switch with 12
ON resistance
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
HP0 to HP10
B5, B8, B10, D10,
G10, K10, K8, K5,
K3, J2, F2
Host ports
EN
C2
LVCMOS level enable input (active LOW). When connected
HIGH, all DIMM ports will be disconnected (show a
high-impedance path) from the Host ports.
STREN
A2
Strobe enable. LVCMOS level strobe enable input
(active HIGH). When tied LOW, channel 10 (HP10 and its
DP ports) functions identically to all other channels. When
tied HIGH, channel 10 is designated as the Strobe channel
S0
B2
Select inputs; type SSTL_18. See Section 6.1 “Function
S1
A1
VREF
C1
Reference voltage for the pseudo-differential SSTL_18
select inputs (S0, S1).
VBIAS
D1
Voltage bias for the DIMM port pull-down resistor (Rpd).
TERM
B1
LVCMOS level input pin activates termination resistance on
Sn inputs when HIGH; high-impedance when LOW.
0DP0, 1DP0,
2DP0, 3DP0
A4, A5,
A6, B6
DIMM port 0
0DP1, 1DP1,
2DP1, 3DP1
B7, A7,
A8, A9
DIMM port 1
0DP2, 1DP2,
2DP2, 3DP2
A10, A11,
B11, C11
DIMM port 2
0DP3, 1DP3,
2DP3, 3DP3
C10, D11,
E10, E11
DIMM port 3
0DP4, 1DP4,
2DP4, 3DP4
F11, G11,
H10, H11
DIMM port 4
0DP5, 1DP5,
2DP5, 3DP5
J11, J10,
K11, L11
DIMM port 5
0DP6, 1DP6,
2DP6, 3DP6
K9, L9,
L8, L7
DIMM port 6
0DP7, 1DP7,
2DP7, 3DP7
K6, L6,
L5, L4
DIMM port 7
0DP8, 1DP8,
2DP8, 3DP8
K4, L3,
L2, L1
DIMM port 8
0DP9, 1DP9,
2DP9, 3DP9
K1, J1,
H2, H1
DIMM port 9
0DP10, 1DP10,
2DP10, 3DP10
G1, F1,
E1, E2
DIMM port 10
GND
B4, B9, D2, F10,
G2, K2, K7
Ground
VDD
A3, B3, L10
Positive supply voltage
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