參數(shù)資料
型號(hào)： CBTL06DP212EE
廠商： NXP SEMICONDUCTORS
元件分類： 編、解碼器及復(fù)用、解復(fù)用
英文描述： High-performance DisplayPort Gen2 2 : 1 multiplexer
中文描述： MULTIPLEXER, PBGA48
封裝： 5 X 5 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, TFBGA-48
文件頁數(shù)： 3/18頁
文件大?。?/td> 147K
代理商： CBTL06DP212EE
CBTL06DP212
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
11 of 18
NXP Semiconductors
CBTL06DP212
High-performance DisplayPort Gen2 2 : 1 multiplexer
12. Application information
12.1 Special considerations
Certain cable or dongle misplug scenarios make it possible for a 5 V input condition to
occur on pins AUX+ and AUX
, as well as HPDIN. When AUX+ and AUX are connected
through a minimum of 2.2 k
Ω each, the CBTL06DP212 will sink current but will not be
damaged. Similarly, HPDIN may be connected to 5 V via at least a 1 k
Ω resistor. (Correct
functional operation to specification is not expected in these scenarios.) The latter also
prevents the HPDIN input from loading down the system HPD signal when power to the
CBTL06DP212 is off.
Fig 4.
Application diagram
OUT_n
HPDIN
OUT_n+
002aaf944
2 : 1
MUX
AUX
AUX+
4 : 1
MUX
2 : 1
MUX
DDC_AUX_SEL
GPU_SEL
CBTL06DP212
DP
CONNECT
OR
IN1_n
IN1_n+
GPU2_DP++ SOURCE
IN2_n
IN2_n+
AUX1
AUX1+
GND
100 k
Ω
VDD
100 k
Ω
AUX2
AUX2+
GND
100 k
Ω
VDD
100 k
Ω
GPU1_DP++
SOURCE
+3.3 V
DDC_DAT1
DDC_CLK1
2 k
Ω
DDC_DAT2
DDC_CLK2
HPD_1
HPD_2
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