參數(shù)資料
型號(hào): CBTL06DP212EE
廠商: NXP SEMICONDUCTORS
元件分類: 編、解碼器及復(fù)用、解復(fù)用
英文描述: High-performance DisplayPort Gen2 2 : 1 multiplexer
中文描述: MULTIPLEXER, PBGA48
封裝: 5 X 5 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, TFBGA-48
文件頁(yè)數(shù): 2/18頁(yè)
文件大?。?/td> 147K
代理商: CBTL06DP212EE
CBTL06DP212
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 February 2011
10 of 18
NXP Semiconductors
CBTL06DP212
High-performance DisplayPort Gen2 2 : 1 multiplexer
11.3 AUX and DDC ports
[1]
Time from DDC/AUX input changing state to AUX output changing state. Includes DDC/AUX rise/fall time.
11.4 HPDIN input, HPD_x outputs
[1]
Time from HPDIN changing state to HPD_x changing state. Includes HPD rise/fall time.
11.5 GPU_SEL and DDC_AUX_SEL inputs
Table 11.
AUX and DDC port characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VI
input voltage
0.3
-
VDD +0.3
V
VO
output voltage
no load
-
VDD
V
VIC
common-mode input voltage
AUX
0
-
2.0
V
VID
differential input voltage
AUX
-
+1.4
V
tPD
propagation delay
from left-side port to right-side
port or vice versa
[1] -80
-
ps
Table 12.
HPD input and output characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VI
input voltage
0.3
-
VDD +0.3
V
VO
output voltage
no load
-
VDD
V
tPD
propagation delay
from HPDIN to HPD_x or vice versa
[1] -80
-
ps
Table 13.
GPU_SEL and DDC_AUX_SEL input characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIH
HIGH-level input voltage
2.0
-
V
VIL
LOW-level input voltage
-
0.8
V
ILI
input leakage current
VDD =3.6 V; 0.3V ≤ VI ≤ 3.9 V
-
10
μA
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