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參數(shù)資料
| 型號(hào)： | CBTL06DP211EE |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 編、解碼器及復(fù)用、解復(fù)用 |
| 英文描述： | DisplayPort Gen1 2 : 1 multiplexer |
| 中文描述： | MULTIPLEXER, PBGA48 |
| 封裝： | 5 X 5 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, TFBGA-48 |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 144K |
| 代理商： | CBTL06DP211EE |
CBTL06DP211
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 1 — 21 February 2011
5 of 18
NXP Semiconductors
CBTL06DP211
DisplayPort Gen1 2 : 1 multiplexer
6.2 Pin description
Table 2.
Pin description
Symbol
Ball
Type
Description
GPU_SEL
A1
3.3 V low-voltage CMOS
single-ended input
Selects between two multiplexer/switch paths. When HIGH, path 2
left-side is connected to its corresponding right-side I/O. When
LOW, path 1 left-side is connected to its corresponding right-side
I/O.
DDC_AUX_SEL
C2
3.3 V low-voltage CMOS
single-ended input
Selects between DDC and AUX paths. When HIGH, the
DDC_CLKn and DDC_DATn I/Os are connected to their respective
AUX terminals. When LOW, the AUX+ and AUX
I/Os are
connected to their respective AUX terminals.
XSD
B7
3.3 V low-voltage CMOS
single-ended input
Shutdown pin. Should be driven HIGH or connected to VDD for
normal operation. When LOW, all paths are switched off
(non-conducting) and supply current consumption is minimized.
TST0
G2
3.3 V low-voltage CMOS
single-ended input
Test pin for NXP use only. Should be tied to ground in normal
operation.
IN1_0+
B4
differential I/O
Four high-speed differential pairs for DisplayPort or PCI Express
signals, path 1, left-side.
IN1_0
A4
differential I/O
IN1_1+
B5
differential I/O
IN1_1
A5
differential I/O
IN1_2+
B6
differential I/O
IN1_2
A6
differential I/O
IN1_3+
A8
differential I/O
IN1_3
A9
differential I/O
IN2_0+
B8
differential I/O
Four high-speed differential pairs for DisplayPort or PCI Express
signals, path 2, left-side.
IN2_0
B9
differential I/O
IN2_1+
D8
differential I/O
IN2_1
D9
differential I/O
IN2_2+
E8
differential I/O
IN2_2
E9
differential I/O
IN2_3+
F8
differential I/O
IN2_3
F9
differential I/O
OUT_0+
B2
differential I/O
Four high-speed differential pairs for DisplayPort or PCI Express
signals, right-side.
OUT_0
B1
differential I/O
OUT_1+
D2
differential I/O
OUT_1
D1
differential I/O
OUT_2+
E2
differential I/O
OUT_2
E1
differential I/O
OUT_3+
F2
differential I/O
OUT_3
F1
differential I/O
AUX1+
H9
differential I/O
High-speed differential pair for AUX signals, path 1, left-side.
AUX1
J9
differential I/O
AUX2+
H6
differential I/O
High-speed differential pair for AUX signals, path 2, left-side.
AUX2
J6
differential I/O
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CBTL06DP211EE,118 | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 GEN 1 2.7 GBPS 6CH 2:1 MULTI/DEMUX RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| CBTL06DP212 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CBTL06DP212 provides an additional level of multiplexing of AUX and DDC signals delivering true flexibility and choice. |
| CBTL06DP212EE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CBTL06DP212 provides an additional level of multiplexing of AUX and DDC signals delivering true flexibility and choice. |
| CBTL06DP212EE,118 | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 GEN 2 5.4 GBPS 6CH 2:1 MULTIPLEXER RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| CBTL06DP213EE,118 | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 DISPLAYPORT MULTIPLEXER RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
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