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參數(shù)資料
| 型號： | CBT3253DS |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | LC2MOS ±15 V Quad SPST Switch; Package: PDIP; No of Pins: 16; Temperature Range: Commercial |
| 中文描述： | DUAL 1 LINE TO 4 LINE MULTIPLEXER AND DEMUX/DECODER, TRUE OUTPUT, PDSO16 |
| 封裝： | 3.90 MM, PLASTIC, SOT-519-1, QSOP-16 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 98K |
| 代理商： | CBT3253DS |
Philips Semiconductors
Product data
CBT3253
Dual 1-of-4 FET multiplexer/demultiplexer
2002 Nov 04
6
AC WAVEFORMS
V
M
= 1.5 V, V
IN
= GND to 3.0 V
INPUT
1.5 V
OUTPUT
t
PLH
t
PHL
1.5 V
1.5 V
1.5 V
3 V
0 V
V
OH
V
OL
SA00591
Waveform 1. Pulse duration
Output
Control
(Low-level
enabling)
1.5 V
t
PZH
t
PHZ
V
OH
V
OL
t
PZL
t
PLZ
3.5 V
0 V
V
OL
+ 0.3V
V
OH
–
0.3V
1.5 V
1.5 V
3 V
Output
Waveform 1
S1 at 4.3 V
(see Note)
Note:
Waveform 1 is for an output with internal conditions such that
the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that
the output is high except when disabled by the output control.
Output
Waveform 2
S1 at Open
(see Note)
0 V
SA00592
1.5 V
Waveform 2. 3-State Output Enable and Disable Times
NOTES:
1. t
PLZ
and t
PHZ
are the same as t
dis
.
2. t
PZL
and t
PZH
are the same as t
en
.
3. t
PLH
and t
PHL
are the same as t
pd
.
TEST CIRCUIT AND WAVEFORMS
C
L
= 50 pF
Load Circuit
DEFINITIONS
C
L
=
Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
TEST
S1
t
pd
open
t
PLZ
/t
PZL
7 V
t
PHZ
/t
PZH
open
SA00590
From Output
Under Test
S1
7 V
Open
GND
500
500
NOTES:
1. All input pulses are supplied by generators having the following
characteristics: PRR
≤
10 MHz, Z
O
= 50
, t
r
≤
2.5 ns, t
f
≤
2.5 ns.
2. The outputs are measured one at a time with one transition per
measurement.
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