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參數(shù)資料
| 型號(hào)： | CAT93C76VI-REVA |
| 元件分類： | PROM |
| 英文描述： | 512 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大小： | 412K |
| 代理商： | CAT93C76VI-REVA |
6
CAT93C76
Doc. No. 1090, Rev. A
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
of tCSMIN. The falling edge of CS will start the self clocking
clear cycle of the selected memory location. The clocking
of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of
the CAT93C76 can be determined by selecting the
device and polling the DO pin. Once cleared, the content
of a cleared location returns to a logical “1” state.
Erase/Write Enable and Disable
The CAT93C76 powers up in the write disable state. Any
writing after power-up or after an EWDS (write disable)
instruction must first be preceded by the EWEN (write
enable) instruction. Once the write instruction is enabled,
it will remain enabled until power to the device is removed,
or the EWDS instruction is sent. The EWDS instruction
can be used to disable all CAT93C76 write and clear
instructions, and will prevent any accidental writing or
clearing of the device. Data can be read normally from
the device regardless of the write enable/disable status.
Erase All
Upon receiving an ERAL command, the CS (Chip Select)
pin must be deselected for a minimum of tCSMIN. The
falling edge of CS will start the self clocking clear cycle
of all memory locations in the device. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C76 can be determined by selecting the device
and polling the DO pin. Once cleared, the contents of all
memory bits return to a logical “1” state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
status of the CAT93C76 can be determined by selecting
the device and polling the DO pin. It is not necessary for
all memory locations to be cleared before the WRAL
command is executed.
Note 1: After the last data bit has been sampled, Chip
Select (CS) must be brought Low before the next rising
edge of the clock (SK) in order to start the self-timed high
voltage cycle. This is important because if CS is brought
low before or after this specific frame window, the
addressed location will not be programmed or erased.
Power-On Reset (POR)
The CAT93C76 incorporates Power-On Reset (POR)
circuitry which protects the device against malfunctioning
while VCC is lower than the recommended operating
voltage.
The device will power up into a read-only state and will
power-down into a reset state when VCC crosses the
POR level of ~1.3 V.
Figure 4. Erase Instruction Timing
SK
CS
DI
DO
STANDBY
HIGH-Z
1
AN
AN-1
BUSY
READY
STATUS VERIFY
tSV
tHZ
tEW
tCS
11
A0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT93C76WGI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
| CAT93C76YGI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
| CAT93C76YGI-T3 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
| CAT93C76YI-G | 功能描述:電可擦除可編程只讀存儲(chǔ)器 (1024x8)/(512x16) 8K RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT93C76YI-GT3 | 功能描述:電可擦除可編程只讀存儲(chǔ)器 8K-Bit Microwire Serial 電可擦除可編程只讀存儲(chǔ)器 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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