參數(shù)資料
型號: CAT93C56VP2I
元件分類: PROM
英文描述: 128 X 16 MICROWIRE BUS SERIAL EEPROM, DSO8
封裝: 2 X 3 MM, GREEN, MO-229, TDFN-8
文件頁數(shù): 18/18頁
文件大?。?/td> 390K
代理商: CAT93C56VP2I
CAT93C56, CAT93C57
Catalyst Semiconductor, Inc.
9
Doc. No. MD-1088 Rev. P
Characteristics subject to change without notice
Erase All
Upon receiving an ERAL command (Figure 6), the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The
ready/busy status of the CAT93C56/57 can be deter-
mined by selecting the device and polling the DO pin.
Once cleared, the contents of all memory bits return to
a logical “1” state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN (Figure 7). The falling edge of CS will start the
self clocking data write to all memory locations in the
device. The clocking of the SK pin is not necessary
after the device has entered the self clocking mode.
The ready/busy status of the CAT93C56/57 can be
determined by selecting the device and polling the DO
pin. It is not necessary for all memory locations to be
cleared before the WRAL command is executed.
Figure 6. ERAL Instruction Timing
Figure 7. WRAL Instruction Timing
SK
CS
DI
DO
STANDBY
tCS
HIGH-Z
10
1
BUSY
READY
STATUS VERIFY
tSV
tHZ
tEW
00
STATUS VERIFY
SK
CS
DI
DO
STANDBY
HIGH-Z
10
1
BUSY
READY
tSV
tHZ
tEW
tCSMIN
DN
D0
0
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