參數(shù)資料
型號: CAT64LC40ZJ-TE13
英文描述: 72-Mbit QDR-II™ SRAM 2-Word Burst Architecture
中文描述: SPI串行EEPROM
文件頁數(shù): 4/11頁
文件大?。?/td> 140K
代理商: CAT64LC40ZJ-TE13
4
CAT64LC10/20/40
Doc. No. 1021, Rev. A
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) This parameter is sampled but not 100% tested.
(3) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
WRITE CYCLE LIMIITS
Symbol
Parameter
Min.
Max.
Units
t
WR
Program Cycle Time
2.5V
10
ms
4.5V–6.0V
5
A.C. OPERATING CHARACTERISTICS
V
CC
= +2.5V to +6.0V, unless otherwise specified.
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
t
CSS
CS
Setup Time
100
ns
t
CSH
CS
Hold Time
100
ns
t
DIS
DI Setup Time
200
ns
t
DIH
DI Hold Time
200
ns
t
PD1
Output Delay to 1
300
ns
t
PD0
Output Delay to 0
300
ns
t
HZ(2)
Output Delay to High Impendance
500
ns
t
CSMIN
Minimum
CS
High Time
250
ns
t
SKHI
Minimum SK High Time
2.5V
1000
ns
4.5V–6.0V
400
t
SKLOW
Minimum SK Low Time
2.5V
1000
ns
4.5V–6.0V
400
t
SV
Output Delay to Status Valid
500
ns
f
SK
Maximum Clock Frequency
2.5V
250
kHz
4.5V–6.0V
1000
t
RESS
Reset to
CS
Setup Time
0
ns
t
RESMIN
Minimum RESET High Time
250
ns
t
RESH
RESET to READY Hold Time
0
ns
t
RC
Write Recovery
100
ns
POWER-UP TIMING
(1)(3)
Symbol
Parameter
Min.
Max.
Units
μ
s
t
PUR
Power-Up to Read Operation
10
t
PUW
Power-Up to Program Operation
1
ms
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