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參數(shù)資料
| 型號： | CAT64LC40UITE13 |
| 英文描述： | 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture |
| 中文描述： | EEPROM的 |
| 文件頁數(shù)： | 3/11頁 |
| 文件大小： | 140K |
| 代理商： | CAT64LC40UITE13 |
3
CAT64LC10/20/40
Doc. No. 1021, Rev. A
D.C. OPERATING CHARACTERISTICS
V
CC
= +2.5V to +6.0V, unless otherwise specified.
Note:
(1) Standby Current (I
SB
) = 0
μ
A (<900nA)
(2) V
OH
and V
OL
spec applies to READY/
BUSY
pin also
Limits
Sym.
Parameter
Min.
Typ.
Max.
Units
Test Conditions
I
CC
Operating Current
2.5V
0.4
mA
f
SK
= 250 kHz
EWEN, EWDS, READ 6.0V
1
mA
f
SK
= 1 MHz
I
CCP
Program Current
2.5V
2
mA
6.0V
3
mA
I
SB(1)
Standby Current
0
μ
A
V
IN
= GND or V
CC
CS = V
CC
I
LI
Input Leakage Current
2
μ
A
μ
A
V
IN
= GND to V
CC
I
LO
Output Leakage Current
10
V
OUT
= GND to V
CC
V
IL
Low Level Input Voltage, DI
–0.1
V
CC
x 0.3
V
V
IH
High Level Input Voltage, DI
V
CC
x 0.7
V
CC
+ 0.5
V
V
IL
Low Level Input Voltage,
CS
, SK, RESET
–0.1
V
CC
x 0.2
V
V
IH
High Level Input Voltage,
CS
, SK, RESET
V
CC
x 0.8
V
CC
+ 0.5
V
V
OH(2)
High Level Output Voltage
2.5V
V
CC
– 0.3
V
I
OH
= –10
μ
A
I
OH
= –10
μ
A
I
OH
= –400
μ
A
I
OL
= 10
μ
A
6.0V
V
CC
– 0.3
V
2.4
V
V
OL(2)
Low Level Output Voltage
2.5V
0.4
V
6.0V
0.4
V
I
OL
= 2.1mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CAT64LC40URATE13 | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| CAT64LC40URITE13 | EEPROM |
| CAT64LC40URTE13 | EEPROM |
| CAT64LC40UTE13 | 72-Mbit QDR™-II SRAM 2-Word Burst Architecture |
| CAT64LC40ZJ | 72-Mbit QDR™-II SRAM 2-Word Burst Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT64LC40URATE13 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:1K/2K/4K-Bit SPI Serial E2PROM |
| CAT64LC40URITE13 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| CAT64LC40URTE13 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| CAT64LC40U-T3 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:4 kb SPI Serial EEPROM |
| CAT64LC40UTE13 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
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