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參數(shù)資料
| 型號(hào)： | CAT64LC20ZJI |
| 英文描述： | 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM |
| 中文描述： | SPI串行EEPROM |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大小： | 140K |
| 代理商： | CAT64LC20ZJI |
5
CAT64LC10/20/40
Doc. No. 1021, Rev. A
INSTRUCTION SET
Instruction
Opcode
Address
Data
Read
64LC10
10101000
A5 A4 A3 A2 A1 A0 0
0
D15 - D0
64LC20
10101000
A6 A5 A4 A3 A2 A1 A0
0
D15 - D0
64LC40
10101000
A7 A6 A5 A4 A3 A2 A1 A0
D15 - D0
Write
64LC10
10100100
A5 A4 A3 A2 A1 A0 0
0
D15 - D0
64LC20
10100100
A6 A5 A4 A3 A2 A1 A0
0
D15 - D0
64LC40
10100100
A7 A6 A5 A4 A3 A2 A1 A0
D15 - D0
Write Enable
10100011
X X X X X X X X
Write Disable
10100000
X X X X X X X X
[Write All Locations]
(1)
10100001
X X X X X X X X
D15–D0
Figure 1. A.C. Testing Input/Output Waveform
(2)(3(4)
(C
L
= 100 pF)
Note:
(1)
(2)
(3)
(4)
(Write All Locations) is a test mode operation and is therefore not included in the A.C./D.C. Operations specifications.
Input Rise and Fall Times (10% to 90%) < 10 ns.
Input Pulse Levels = V
CC
x 0.2 and V
CC
x 0.8.
Input and Output Timing Reference = V
CC
x 0.3 and V
CC
x 0.7.
INPUT PULSE LEVELS
REFERENCE POINTS
VCC x 0.7
VCC x 0.3
VCC x 0.8
VCC x 0.2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CAT64LC20ZJI-TE13 | SPI Serial EEPROM |
| CAT64LC20ZJI-TE7 | 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CAT64LC20ZJ-TE13 | 256K (32K x 8) Static RAM |
| CAT64LC20ZJ-TE7 | 256K (32K x 8) Static RAM |
| CAT64LC20ZP | 36-Mbit QDR™-II SRAM 2-Word Burst Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT64LC20ZJI-TE13 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM |
| CAT64LC20ZJI-TE7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM |
| CAT64LC20ZJ-TE13 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM |
| CAT64LC20ZJ-TE7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM |
| CAT64LC20ZP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM |
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