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參數(shù)資料
| 型號： | CAT64LC10JI-TE13 |
| 英文描述： | 36-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| 中文描述： | SPI串行EEPROM |
| 文件頁數(shù)： | 6/11頁 |
| 文件大小： | 140K |
| 代理商： | CAT64LC10JI-TE13 |
6
CAT64LC10/20/40
Doc. No. 1021, Rev. A
DEVICE OPERATION
The CAT64LC10/20/40 is a 1K/2K/4K-bit nonvolatile
memory intended for use with all standard controllers.
The CAT64LC10/20/40 is organized in a 64/128/256 x
16 format. All instructions are based on an 8-bit format.
There are four 16-bit instructions: READ, WRITE, EWEN,
and EWDS. The CAT64LC10/20/40 operates on a single
power supply ranging from 2.5V to 6.0V and it has an on-
chip voltage generator to provide the high voltage needed
during a programming operation. Instructions, addresses
and data to be written are clocked into the DI pin on the
rising edge of the SK clock. The DO pin is normally in a
high impedance state except when outputting data in a
READ operation or outputting RDY/
BSY
status when
polled during a WRITE operation.
The format for all instructions sent to this device includes
a 4-bit start sequence, 1010, a 4-bit op code and an 8-
bit address field or dummy bits. For a WRITE operation,
Figure 2. Sychronous Data Timing
Figure 3. Read Instruction Timing
* Please check the instruction set table for address
SK
DI
CS
DO
tPD0,tPD1
tCSS
tDIS
tSKHI
tSKLOW
RESET
RDY/
BUSY
tRESS
tRC
tDIH
tCSH
tCSMIN
tHZ
tSV
tSV
tRESH
SK
DI
CS
DO
RESET
1
0
1
0
1
0
0
0
ADDRESS*
D15 D14
D1
D0
HIGH
RDY/
BUSY
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CAT64LC10JI-TE7 | 36-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CAT64LC10J-TE13 | 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| CAT64LC10J-TE7 | 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| CAT64LC10P | 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| CAT64LC10P-2.5 | 2K x 8 Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT64LC10JI-TE7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM |
| CAT64LC10JTE13 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:1K/2K/4K-Bit SPI Serial E2PROM |
| CAT64LC10J-TE13 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM |
| CAT64LC10J-TE7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM |
| CAT64LC10L | 功能描述:電可擦除可編程只讀存儲器 64 X 16 1K 2.5-6.0 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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