參數(shù)資料
型號(hào)： CAT25CXXX
英文描述： Supervisory Circuits with SPI Serial E2PROM, Precision Reset Controller and Watchdog Timer
中文描述： 監(jiān)控電路具有SPI串行E2PROM，精密復(fù)位控制器和看門狗定時(shí)器
文件頁(yè)數(shù)： 10/10頁(yè)
文件大?。?/td> 77K
代理商： CAT25CXXX
9
CAT25010/20/40
Doc. No. 1006, Rev. G
Figure 9.
HOLD
HOLD Timing
DESIGN CONSIDERATIONS
The CAT250140/20/40 powers up in a write disable
state and in a low power standby mode. A WREN
instruction must be issued to perform any writes to the
device after power up. Also,on power up
CS should be
brought low to enter a ready state and receive an
instruction. After a successful byte/page write or status
register write, the CAT250140/20/40 goes into a write
disable mode.
CS must be set high after the proper
Figure 8. Page Write Instruction Timing
Note: Dashed Line= mode (1, 1) – ––––
*X=0 for 25010, 25020 ; X=A8 for 25040
Note: Dashed Line= mode (1, 1) – ––––
CS
SCK
HOLD
SO
tCD
tHD
tCD
tLZ
tHZ
HIGH IMPEDANCE
Figure 10.
WP
WP Timing
Note: Dashed Line= mode (1, 1) – ––––
number of clock cycles to start an internal write cycle.
Access to the array during an internal write cycle is
ignored and programming is continued. On power up,
SO is in a high impedance. If an invalid op code is
received, no data will be shifted into the CAT250140/
20/40, and the serial output pin (SO) will remain in a
high impedance state until the falling edge of
CS is
detected again.
SK
SI
SO
00
10
ADDRESS
Data
Byte 1
012345678
21
22
23 24-31
32-39
Data
Byte 2
Data
Byte 3
Data Byte N
CS
OPCODE
7..1
0
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
DATA IN
HIGH IMPEDANCE
CS
SCK
WP
tWPS
tWPH
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CAT25LV65-25 制造商:Catalyst Semiconductor 功能描述:
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CAT25M01VI-G 制造商:ON Semiconductor 功能描述:1MB SPI SER CMOS EEPROM - Rail/Tube
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CAT25M01XI 制造商:ON Semiconductor 功能描述:1MB SPI SER CMOS EEPROM - Rail/Tube 制造商:ON Semiconductor 功能描述:TUBE / 1MB SPI SER CMOS EEPROM
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