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參數(shù)資料
| 型號： | CAT24WC05RI-1.8TE13REV-A |
| 元件分類： | PROM |
| 英文描述： | 512 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封裝： | MO-187AA, MSOP-8 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 216K |
| 代理商： | CAT24WC05RI-1.8TE13REV-A |
CAT24WC03/05
7
Doc. No. 1005, Rev. G
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the upper half (locations 80H
to FFH for CAT24WC03 and locations 100H to 1FFH for
CAT24WC05) of the memory array is protected and
becomes read only. The CAT24WC03/05 will accept
both slave and byte addresses, but the memory location
accessed is protected from programming by the device’s
failure to send an acknowledge after the first byte of data
is received.
READ OPERATIONS
The READ operation for the CAT24WC03/05 is initiated
in the same manner as the write operation with the one
exception that the R/
W bit is set to a one. Three different
READ operations are possible: Immediate Address
READ, Selective READ and Sequential READ.
Immediate Address Read
The CAT24WC03/05 address counter contains the
address of the last byte accessed incremented by one.
In other words, if the last READ or WRITE access was
to address N, the READ immediately following would
access data from address N+1. If N=E (where E = 255
for the CAT24WC03 and 511 for the CAT24WC05), then
the counter will ‘wrap around’ to address 0 and continue
to clock out data. After the CAT24WC03/05 receives its
slave address information (with the R/
W bit set to one),
it issues an acknowledge, then transmits the 8-bit byte
requested. The master device does not send an
acknowledge but will generate a STOP condition.
Selective Read
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte address of the location it wishes to
read. After the CAT24WC03/05 acknowledge the word
address, the Master device resends the START condition
and the slave address, this time with the R/
W bit set to
one. The CAT24WC03/05 then responds with its
acknowledge and sends the 8-bit byte requested. The
master device does not send an acknowledge but will
generate a STOP condition.
Figure 8. Immediate Address Read Timing
SCL
SDA
8TH BIT
STOP
NO ACK
DATA OUT
89
SLAVE
ADDRESS
S
A
C
K
DATA
N
O
A
C
K
S
T
O
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
Figure 9. Selective Read Timing
SLAVE
ADDRESS
S
A
C
K
N
O
A
C
K
S
T
O
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
BYTE
ADDRESS (n)
S
A
C
K
DATA n
SLAVE
ADDRESS
A
C
K
S
T
A
R
T
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CAT24WC05U | 功能描述:電可擦除可編程只讀存儲器 (512x8) 4k 2.5-6.0 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT24WC05U-1.8 | 功能描述:電可擦除可編程只讀存儲器 (512x8) 4k 1.8-6.0 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT24WC05UA | 功能描述:電可擦除可編程只讀存儲器 (512x8) 4k 2.5-6.0 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT24WC05UI | 功能描述:電可擦除可編程只讀存儲器 (512x8) 4k 2.5-6.0 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT24WC05UI-1.8 | 功能描述:電可擦除可編程只讀存儲器 (512x8) 4k 1.8-6.0 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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