參數(shù)資料
型號: CAT24FC64GLETE13
元件分類: EEPROM
英文描述: 64K-Bit I2C Serial CMOS EEPROM
中文描述: 64K的位I2C串行CMOS EEPROM的
文件頁數(shù): 3/10頁
文件大小: 635K
代理商: CAT24FC64GLETE13
DsconinuedPat
Note:
(1) AC measurement conditions:
RL (connects to V
CC
): 0.3V
CC
to 0.7 V
CC
Input rise and fall times: < 50ns
Input and output timing reference voltages: 0.5 V
CC
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
CAT24FC64
3
Doc No. 1046, Rev. K
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
A.C. CHARACTERISTICS
V
CC
= +2.5V to +5.5V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Power-Up Timing
(2)(3)
Symbol
Parameter
Min
Typ
Max
Units
PUR
Power-Up to Read Operation
100
μ
μ
PUW
Power-Up to Write Operation
100
l
b
m
y
S
r
e
m
a
r
a
P
V
5
-
V
5
=
C
C
V
n
M
x
a
M
s
U
L
C
S
A
A
O
K
C
A
O
A
S
w
L
L
C
S
0
5
0
0
9
F
U
B
)
C
m
T
w
N
B
F
b
M
B
h
m
S
0
0
3
1
A
T
S
:
H
m
H
C
S
0
0
6
W
O
L
w
L
k
C
0
0
3
1
H
G
I
H
h
g
H
k
C
0
0
6
A
T
S
:
U
S
)
C
S
p
R
r
m
p
S
C
S
0
0
6
T
A
:
H
m
H
0
T
A
:
U
S
m
p
S
0
0
1
R
)
m
R
L
C
S
A
S
0
0
3
F
)
m
l
F
L
C
S
A
S
0
0
3
O
T
S
:
U
S
m
p
S
C
p
S
0
0
6
H
m
H
O
0
5
R
W
m
y
C
W
5
m
S
)
C
S
,
A
S
(
p
S
p
0
5
W
;
U
S
m
p
S
W
0
0
6
W
;
H
m
H
W
0
0
3
1
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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