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參數(shù)資料
| 型號(hào)： | CAT24C21ZDRI-GT3 |
| 元件分類(lèi)： | PROM |
| 英文描述： | 128 X 8 I2C/2-WIRE SERIAL EEPROM, DSO8 |
| 封裝： | 3 X 3 MM, ROHS COMPLIANT, TDSN-8 |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大?。?/td> | 104K |
| 代理商： | CAT24C21ZDRI-GT3 |
CAT24C21
6
Doc. No. MD-1032, Rev. P
Figure 4. Bus Timing
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH
Figure 5. Write Cycle Timing
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge (ACK). The
acknowledging device pulls down the SDA line during the
ninth clock cycle, signaling that it has received the 8 bits of
data (Figure 7).
The CAT24C21 responds with an ACK after receiving a
START condition and its slave address. If the device has
been selected along with a write operation, it responds
with an ACK after receiving each 8-bit byte.
When the CAT24C21 is in a READ mode it transmits 8
bits of data, releases the SDA line, and monitors the line
for an ACK. Once it receives this ACK, the CAT24C21
will continue to transmit data. If no ACK is sent by the
Master, the device terminates data transmission and
waits for a STOP condition.
Write Operations
VCLK must be held high in order to program the device.
This applies to byte write and page write operation.
Once the device is in its self-timed program cycle,
VCLK can go low and not affect programming.
Byte Write
In the Byte Write mode (Figure 9), the Master device
sends the START condition and the slave address
information (with the R/
W bit set to zero) to the Slave
device. After the Slave generates an ACK, the Master
sends the byte address that is to be written into the
address pointer of the CAT24C21. After receiving another
ACK from the Slave, the Master device transmits the
data byte to be written into the addressed memory
location. The CAT24C21 acknowledges once more and
the Master generates the STOP condition, at which time
the device begins its internal programming cycle to
nonvolatile memory (Figure 5). While this internal cycle
is in progress, the device will not respond to any request
from the Master device.
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8th Bit
Byte n
SCL
SDA
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT24C21ZI | 制造商:Catalyst Semiconductor 功能描述: |
| CAT24C256HU4IGT3 | 功能描述:電可擦除可編程只讀存儲(chǔ)器 LOW-SATURATION VOLTAGE RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT24C256LGI | 制造商:Catalyst Semiconductor 功能描述: |
| CAT24C256LI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
| CAT24C256LI-G | 功能描述:電可擦除可編程只讀存儲(chǔ)器 (32768x8) 256K RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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