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參數(shù)資料
| 型號： | CAT24C21ZDRI-GT3 |
| 元件分類： | PROM |
| 英文描述： | 128 X 8 I2C/2-WIRE SERIAL EEPROM, DSO8 |
| 封裝： | 3 X 3 MM, ROHS COMPLIANT, TDSN-8 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 104K |
| 代理商： | CAT24C21ZDRI-GT3 |
CAT24C21
4
Doc. No. MD-1032, Rev. P
PIN DESCRIPTION
The SCL serial clock input pin is used to clock all data
transfers into or out of the device when in the
bi-directional mode.
The SDA bi-directional serial data/address pin is used to
transfer data into and out of the device. The SDA pin is
an open drain output and can be wire-ORed with other
open drain or open collector outputs.
FUNCTIONAL DESCRIPTION
The CAT24C21 has two modes of operation: the transmit-
only mode and the bi-directional mode. There is a
separate 2-wire protocol to support each mode, each
having a separate clock input (VCLK and SCL
respectively) and both modes sharing a common bi-
directional data line (SDA). The CAT24C21 enters the
transmit-only mode upon power up and begins outputting
data on the SDA pin with each clock signal on the VCLK
pin. The device will remain in the transmit-only mode
until there is a valid HIGH to LOW transition on the SCL
pin, when it will switch to the bi-directional mode (Figure
1). Once in the bi-directinal mode, the only way to return
to the transmit-only mode is by powering down the
device.
The VCLK serial clock input pin is used to clock data out
of the device when in transmit-only mode. When held
low, in bi-directional mode, it will inhibit write operations.
TRANSMIT-ONLY MODE: (DDC1)
Upon power-up, the CAT24C21 will output valid data
only after it has been initialized. During initialization,
data will not be available until after the first nine clocks
are sent to the device (Figure 2). The starting address for
the transmit-only mode can be determined during
initialization. If the SDA pin is high during the first eight
clocks, the starting address will be 7FH. If the SDA pin
is low during the first eight clocks, the starting address
will be 00H. During the ninth clock, SDA will be in the high
impedance state.
Data is transmitted in 8 bit words with the most significant
bit first, followed by a 9th 'don't care' bit which will be in
the high impedance state (Figure 3). The CAT24C21 will
continuously sequence through the entire memory array
as long as VCLK is present and no falling edges on SCL
are detected. When the maximum address (7FH) is
reached, addressing will wrap around to the zero location
(00H) and transmitting will continue. The bi-directional
mode clock (SCL) pin must be held high for the device
to remain in the transmit-only mode.
Figure 1. Mode Transition
SCL
SDA
VCLK
Transmit-Only Mode
Bi-Directional Mode
TVHZ
SCL
SDA
VCLK
SDA at high impedance for 9 clock cycles
Bit8
Bit7
Bit6
Bit5
Bit4
TVPU
TVAA
123
4
5
6
7
8
9
10
11
12
13
14
15
Figure 2. Device Initialization for Transmit-only Mode
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT24C21ZI | 制造商:Catalyst Semiconductor 功能描述: |
| CAT24C256HU4IGT3 | 功能描述:電可擦除可編程只讀存儲器 LOW-SATURATION VOLTAGE RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT24C256LGI | 制造商:Catalyst Semiconductor 功能描述: |
| CAT24C256LI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
| CAT24C256LI-G | 功能描述:電可擦除可編程只讀存儲器 (32768x8) 256K RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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