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參數(shù)資料
| 型號(hào)： | CAT24C128WE-T3 |
| 元件分類： | PROM |
| 英文描述： | 16K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, MS-012, SOIC-8 |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 460K |
| 代理商： | CAT24C128WE-T3 |
CAT24C128
6
Doc. No. MD-1103, Rev. J
Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
WRITE OPERATIONS
Byte Write
Upon receiving a Slave address with the R/W bit set
to ‘0’, the CAT24C128 will interpret the next two bytes
as address bytes These bytes are used to initialize the
internal address counter; the 2 most signicant bits are
‘don’t care’, the next 8 point to one of 256 available pages
and the last 6 point to a location within a 64 byte page.
A byte following the address bytes will be interpreted as
data. The data will be loaded into the Page Write Buffer
and will eventually be written to memory at the address
specied by the 14 active address bits provided earlier.
The CAT24C128 will acknowledge the Slave address,
address bytes and data byte. The Master then starts
the internal Write cycle by issuing a STOP condition
(Figure 5). During the internal Write cycle (tWR), the SDA
output will be tri-stated and additional Read or Write
requests will be ignored (Figure 6).
Page Write
By continuing to load data into the Page Write Buffer
after the 1st data byte and before issuing the STOP
condition, up to 64 bytes can be written simultaneously
during one internal Write cycle (Figure 7). If more data
bytes are loaded than locations available to the end of
page, then loading will continue from the beginning of
page, i.e. the page address is latched and the address
count automatically increments to and then wraps-
around at the page boundary. Previously loaded data
can thus be overwritten by new data. What is eventually
written to memory reects the latest Page Write Buffer
contents. Only data loaded within the most recent Page
Write sequence will be written to memory.
Acknowledge Polling
The ready/busy status of the CAT24C128 can be ascer-
tained by sending Read or Write requests immediately
following the STOP condition that initiated the internal
Write cycle. As long as internal Write is in progress, the
CAT24C128 will not acknowledge the Slave address.
Hardware Write Protection
With the WP pin held HIGH, the entire memory
is protected against Write operations. If the WP
pin is left floating or is grounded, it has no im-
pact on the operation of the CAT24C128. The
state of the WP pin is strobed on the last falling
edge of SCL immediately preceding the rst data byte
(Figure 8). If the WP pin is HIGH during the strobe in-
terval, the CAT24C128 will not acknowledge the data
byte and the Write request will be rejected.
Delivery State
The CAT24C128 is shipped erased, i.e., all bytes are
FFh.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT24C128WGE | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
| CAT24C128WGI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
| CAT24C128WI-G | 功能描述:電可擦除可編程只讀存儲(chǔ)器 (16384x8) 128K RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT24C128WI-GT3 | 功能描述:電可擦除可編程只讀存儲(chǔ)器 128K-Bit I2C Serial CMOS 電可擦除可編程只讀存儲(chǔ)器 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT24C128WI-GT3 | 制造商:ON Semiconductor 功能描述:IC EEPROM 128KBIT SERIAL 400KHZ SOIC-8 |
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