參數(shù)資料
型號: CAP1028-1-BP-TR
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, QCC20
封裝: 4 X 4 MM, ROHS COMPLAINT, QFN-20
文件頁數(shù): 10/69頁
文件大?。?/td> 948K
代理商: CAP1028-1-BP-TR
8 Channel Capacitive Touch Sensor with 2 LED Drivers
Datasheet
Revision 1.0 (06-16-09)
18
SMSC CAP1028
DATASHEET
3.3.6
SMBus Receive Byte
The Receive Byte protocol is used to read data from a register when the internal register address
pointer is known to be at the right location (e.g. set via Send Byte). This is used for consecutive reads
of the same register as shown in Table 3.8.
3.4
SPI Interface
The SMBus has a predefined packet structure, the SPI does not. The SPI Bus can operate in two
modes of operation, normal 4-wire mode and bi-directional 3-wire mode. All SPI commands consist of
8-bit packets set to a specific slave device (identified by the CS pin).
The SPI bus will latch data on the rising edge of the clock and the clock and data both idle high.
All commands are supported via both operating modes. The supported commands are: Reset Serial
interface, set address pointer, write command and read command. Note that all other codes received
during the command phase are ignored and have no effect on the operation of the device.
3.4.1
SPI Normal Mode
The SPI Bus can operate in two modes of operation, normal and bi-directional mode. In the normal
mode of operation, there are dedicated input and output data lines. The host communicates by sending
a command along the CAP1028 SPI_MOSI data line and reading data on the SPI_MISO data line.
Both communications occur simultaneously which allows for larger through put of data transactions.
All basic transfers consist of two 8 bit transactions from the Master device while the slave device is
simultaneously sending data at the current address pointer value.
Data writes consist of two or more 8-bit transactions. The host sends a specific write command
followed by the data to write the address pointer. Data reads consist of one or more 8-bit transactions.
Table 3.8 Receive Byte Protocol
START
SLAVE
ADDRESS
RD
ACK
REGISTER DATA
NACK
STOP
1 -> 0
YYYY_YYY
1
0
XXh
1
0 -> 1
Figure 3.1 SPI Timing
SPI_MSIO or
SPI_MOSI or
SPI_MISO
SPI_CLK
tLOW
tRISE
tHIGH
tFALL
tD:CLK
tHD:DAT
tSU:DAT
tP
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