參數(shù)資料
型號(hào): CA3130E
廠商: Intersil
文件頁(yè)數(shù): 16/17頁(yè)
文件大小: 0K
描述: IC OPAMP BIMOS SGL 15MHZ 8-DIP
標(biāo)準(zhǔn)包裝: 50
放大器類型: 通用
電路數(shù): 1
轉(zhuǎn)換速率: 30 V/µs
增益帶寬積: 15MHz
電流 - 輸入偏壓: 5pA
電壓 - 輸入偏移: 8000µV
電流 - 電源: 10mA
電流 - 輸出 / 通道: 45mA
電壓 - 電源,單路/雙路(±): 5 V ~ 16 V,±2.5 V ~ 8 V
工作溫度: -55°C ~ 125°C
安裝類型: 通孔
封裝/外殼: 8-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 8-PDIP
包裝: 管件
其它名稱: CA3130
8
values of source resistance very much greater than 1M
,
the total noise voltage generated can be dominated by the
thermal noise contributions of both the feedback and source
resistors.
Typical Applications
Voltage Followers
Operational amplifiers with very high input resistances, like
the CA3130, are particularly suited to service as voltage
followers. Figure 8 shows the circuit of a classical voltage
follower, together with pertinent waveforms using the
CA3130 in a split-supply configuration.
A voltage follower, operated from a single supply, is shown in
Figure 9, together with related waveforms. This follower
circuit is linear over a wide dynamic range, as illustrated by
the reproduction of the output waveform in Figure 9A with
input-signal ramping. The waveforms in Figure 9B show that
the follower does not lose its input-to-output phase-sense,
even though the input is being swung 7.5V below ground
potential. This unique characteristic is an important attribute
in both operational amplifier and comparator applications.
Figure 9B also shows the manner in which the CMOS output
stage permits the output signal to swing down to the
negative supply-rail potential (i.e., ground in the case
shown). The digital-to-analog converter (DAC) circuit,
described later, illustrates the practical use of the CA3130 in
a single-supply voltage-follower application.
9-Bit CMOS DAC
A typical circuit of a 9-bit Digital-to-Analog Converter (DAC)
is shown in Figure 10. This system combines the concepts of
multiple-switch CMOS lCs, a low-cost ladder network of
discrete metal-oxide-film resistors, a CA3130 op amp
connected as a follower, and an inexpensive monolithic
regulator in a simple single power-supply arrangement. An
additional feature of the DAC is that it is readily interfaced
with CMOS input logic, e.g., 10V logic levels are used in the
circuit of Figure 10.
The circuit uses an R/2R voltage-ladder network, with the
output potential obtained directly by terminating the ladder
arms at either the positive or the negative power-supply
terminal. Each CD4007A contains three “inverters”, each
“inverter” functioning as a single-pole double-throw switch to
terminate an arm of the R/2R network at either the positive
or negative power-supply terminal. The resistor ladder is an
assembly of 1% tolerance metal-oxide film resistors. The five
arms requiring the highest accuracy are assembled with
series and parallel combinations of 806,000
resistors from
the same manufacturing lot.
A single 15V supply provides a positive bus for the CA3130
follower amplifier and feeds the CA3085 voltage regulator. A
“scale-adjust” function is provided by the regulator output
control, set to a nominal 10V level in this system. The line-
voltage regulation (approximately 0.2%) permits a 9-bit
accuracy to be maintained with variations of several volts in
the supply. The flexibility afforded by the CMOS building
blocks simplifies the design of DAC systems tailored to
particular needs.
Single-Supply, Absolute-Value, Ideal Full-Wave
Rectifier
The absolute-value circuit using the CA3130 is shown in
Figure 11. During positive excursions, the input signal is fed
through the feedback network directly to the output.
Simultaneously, the positive excursion of the input signal
also drives the output terminal (No. 6) of the inverting
amplifier in a negative-going excursion such that the 1N914
diode effectively disconnects the amplifier from the signal
path. During a negative-going excursion of the input signal,
the CA3130 functions as a normal inverting amplifier with a
gain equal to -R2/R1. When the equality of the two equations
shown in Figure 11 is satisfied, the full-wave output is
symmetrical.
Peak Detectors
Peak-detector circuits are easily implemented with the
CA3130, as illustrated in Figure 12 for both the peak-positive
and the peak-negative circuit. It should be noted that with
large-signal inputs, the bandwidth of the peak-negative
circuit is much less than that of the peak-positive circuit. The
second stage of the CA3130 limits the bandwidth in this
case. Negative-going output-signal excursion requires a
positive-going signal excursion at the collector of transistor
Q11, which is loaded by the intrinsic capacitance of the
associated circuitry in this mode. On the other hand, during
a negative-going signal excursion at the collector of Q11, the
transistor functions in an active “pull-down” mode so that the
intrinsic capacitance can be discharged more expeditiously.
3
2
1
8
4
7
6
+
-
Rs
1M
47pF -7.5V
0.01
F
+7.5V
0.01
F
NOISE
VOLTAGE
OUTPUT
30.1k
1k
BW (-3dB) = 200kHz
TOTAL NOISE VOLTAGE (REFERRED
TO INPUT) = 23
V (TYP)
FIGURE 7. TEST-CIRCUIT AMPLIFIER (30-dB GAIN) USED
FOR WIDEBAND NOISE MEASUREMENTS
CA3130, CA3130A
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