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參數(shù)資料
| 型號(hào)： | C9811X2AYB |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | CPU系統(tǒng)時(shí)鐘發(fā)生器| SSOP封裝| 56PIN |塑料 |
| 文件頁(yè)數(shù)： | 1/17頁(yè) |
| 文件大?。?/td> | 232K |
| 代理商： | C9811X2AYB |
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Low EMI Clock Generator for Intel
810 Chipset Systems
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07052 Rev. **
05/03/2001
Page 1 of 17
APPROVED PRODUCT
C9811x2
Product Features
Intel’s 810 clock solution
3 copies of CPU Clock (CPU[0:1] and CPU_ITP)
9 copies of SDRAM Clock (SDRAM[0:7] and DCLK)
8 copies of PCI clock
2 copies of 3V66 Clock
2 copies of APIC Clock, synchronous to PCI Clock
1 REF Clock
2 USB Clocks (Non SSC)
Power Down Feature
Spread Spectrum Support
SMBUS Support for turning off unused clocks
56 Pin SSOP Package
Block Diagram
Fig.1
Frequency Table (MHz)
SEL1
SEL0
0
0
0
1
1
0
1
1
CPU
Tri-state
SDRAM
Tri-state
PCI
Tri-state
Test mode (see table2)
66.6
100
100
100
Table 1
33.3
33.3
Note: The following clocks remain fixed frequencies
except in Test Mode.
3V66=66.6MHz, USB/DOT=48MHz, REF=14.318MHz
and IOAPIC=16.6 or 33.3MHz depending on power up
selection.
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
XIN
VDD
SEL1
XOUT
VSS
VSS
3V660
3V661
VDD
VDD
PCI0_ICH
PCI1
PCI2
VSS
PCI3
PCI4
VSS
PCI5
PCI6
PCI7
VDD
VDDA
VSSA
VSS
USB0
USB1
VDD
SEL0
VDD
PD#
DCLK
VSS
SDRAM7
SDRAM6
SDRAM5
VDD
VSS
SDRAM4
SDRAM2
SDRAM3
VDD
SDRAM0
SDRAM1
VSS
CPU2_ITP
VSS
CPU1
VDDC
CPU0
VDDI
IOAPIC1
IOAPIC0
VSS
C9811X2
ASEL/REF
SDATA
SCLK
49
50
51
52
53
54
55
56
VDDC
VDDS
VDD
VDD
VDDI
VDD
VDD
PLL1
Rin
i2c-clk
i2c-data
apic
s1
s0
pwr_dwn#
cpu
sdram
66m
pci
PLL2
Rin
48
PD#
i2c-clk
i2c-data
300K
36pF
36pF
X
B
U
F
3
9
2
8
2
1
1
XIN
XOUT
CPU(0:2)
SDRAM(0:7), DCLK
3V66(0:1)
PCI(0:7)
IOAPIC(0:1)
SDATA
SCLK
PD#
SEL0
SEL1
USB (0:1)
REF
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