PCIX I/O System Clock Generator With EMI Control Features
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07034 Rev. **
05/02/2001
Page 9 of 14
APPROVED PRODUCT
C9531
AC Parameters
Output Frequency
Symbol
Parameter
133 MHz
100 MHz
66 MHz
33 MHz
Units
Notes
Min
7.0
3
3
0.50
-
Max
8.0
-
-
1.33
250
Min
9.5
4
4
0.50
-
Max
10.5
-
-
1.33
250
Min
14.5
6
6
0.50
-
Max
15.5
-
-
1.33
250
Min
29.5
11
11
0.50
-
Max
30.5
-
-
1.33
250
Tcyc
THIGH
TLOW
Tr / Tf
TSKEW
CLK(0:4) period
CLK(0:4) period
CLK(0:4) low time
CLK(0:4) rise and fall times
(Any CLK ) to (Any CLK)
Skew time
CLK(0:4) Cycle to Cycle
Jitter
REFOUT rise and fall times
REFOUT Cycle to Cycle
Jitter
OE to clock enable delay (all
outputs)
OE to clock disable delay (all
outputs)
All clock Stabilization from
power-up
This parameter is measured as an average over 1uS duration, with an input frequency of 33.333 MHz
All outputs loaded as per table 1 below.
Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V (see Fig.6A and Fig.6B)
Probes are placed on the pins, and measurements are acquired at 1.5V. (See Figs.6A & 6B)
This measurement is applicable with Spread ON or OFF.
Probes are placed on the pins, and measurements are acquired at 2.4Vs, (see Figs. 6A & 6B)
Probes are placed on the pins, and measurements are acquired at 0.4V.
The time specified is measured from when all VDD’s reach their respective supply rail (3.3V) till the frequency output is stable and operating
within the specifications
Applicable only to clocks within the same bank
ns
ns
ns
ns
ps
1, 2, 4
2,6
2, 7
2, 3
2, 4,
5.9
2, 4, 5
TCCJ
-
175
-
175
-
175
-
175
ps
Tr / Tf
TCCJ
1.0
4.0
1.0
4.0
1.0
4.0
1.0
4.0
ns
pS
2, 3
2, 4
750
tpZL, tpZH
-
10.0
-
10.0
-
10.0
-
10.0
ns
tpLZ, tpHZ
-
10.0
-
10.0
-
10.0
-
10.0
ns
tstable
-
3
-
3
-
3
-
3
ms
8
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Output Name
CLK(0:4)
REF
Max Load (in pF)
30
20
Table 1