Rev. 1.4
73
C8051F52x/F53x
Important Note About the VREF Pin: Port pin P0.0 is used as the external VREF input and as an output for
the internal VREF. When using either an external voltage reference or the internal reference circuitry, P0.0
should be configured as an analog pin, and skipped by the Digital Crossbar. To configure P0.0 as an ana-
log pin, clear Bit 0 in register P0MDIN to 0. To configure the Crossbar to skip P0.0, set Bit 0 in register
details.
The TEMPE bit in register REF0CN enables/disables the temperature sensor. While disabled, the temper-
ature sensor defaults to a high impedance state and any ADC0 measurements performed on the sensor
result in meaningless data.
SFR Definition 5.1. REF0CN: Reference Control
Bits7–6: RESERVED. Read = 00b. Must write 00b.
Bit5:
ZTCEN: Zero-TempCo Bias Enable Bit*.
0: ZeroTC Bias Generator automatically enabled when needed.
1: ZeroTC Bias Generator forced on.
Bit4:
REFLV: Voltage Reference Output Level Select.
This bit selects the output voltage level for the internal voltage reference.
0: Internal voltage reference set to 1.5 V.
1: Internal voltage reference set to 2.2 V.
Bit3:
REFSL: Voltage Reference Select.
This bit selects the source for the internal voltage reference.
0: VREF pin used as voltage reference.
1: VDD used as voltage reference.
Bit2:
TEMPE: Temperature Sensor Enable Bit.
0: Internal Temperature Sensor off.
1: Internal Temperature Sensor on.
Bit1:
BIASE: Internal Analog Bias Generator Enable Bit.
0: Internal Analog Bias Generator automatically enabled when needed.
1: Internal Analog Bias Generator on.
Bit0:
REFBE: Internal Reference Buffer Enable Bit.
0: Internal Reference Buffer disabled.
1: Internal Reference Buffer enabled. Internal voltage reference driven on the VREF pin.
older silicon revisions.
R/W
Reset Value
Reserved Reserved
ZTCEN
REFLV
REFSL
TEMPE
BIASE
REFBE
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xD1