參數(shù)資料
型號(hào): C8051F531A-IT
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 171/220頁(yè)
文件大小: 0K
描述: IC 8051 MCU 8K FLASH 20TSSOP
產(chǎn)品培訓(xùn)模塊: Serial Communication Overview
標(biāo)準(zhǔn)包裝: 74
系列: C8051F53x
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 16
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 622 (CN2011-ZH PDF)
配用: 336-1488-ND - KIT DEV C8051F53XA, C8051F52XA
336-1457-ND - ADAPTER PROG TOOLSTICK F530TPP
336-1456-ND - ADAPTER PROG TOOLSTICK F530MPP
其它名稱(chēng): 336-1496-5
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C8051F52x/F53x
54
Rev. 1.4
4.3. ADC0 Operation
In a typical system, ADC0 is configured using the following steps:
1. If a gain adjustment is required, refer to Section “4.4. Selectable Gain” on page 60.
2. Choose the start of conversion source.
3. Choose Normal Mode or Burst Mode operation.
4. If Burst Mode, choose the ADC0 Idle Power State and set the Power-Up Time.
5. Choose the tracking mode. Note that Pre-Tracking Mode can only be used with Normal Mode.
6. Calculate required settling time and set the post convert-start tracking time using the AD0TK bits.
7. Choose the repeat count.
8. Choose the output word justification (Right-Justified or Left-Justified).
9. Enable or disable the End of Conversion and Window Comparator Interrupts.
4.3.1. Starting a Conversion
A conversion can be initiated in one of four ways, depending on the programmed states of the ADC0 Start
of Conversion Mode bits (AD0CM1–0) in register ADC0CN. Conversions may be initiated by one of the fol-
lowing:
Writing a 1 to the AD0BUSY bit of register ADC0CN
A rising edge on the CNVSTR input signal (pin P0.6)
A Timer 1 overflow (i.e., timed continuous conversions)
A Timer 2 overflow (i.e., timed continuous conversions)
Writing a 1 to AD0BUSY provides software control of ADC0 whereby conversions are performed "on-
demand.” During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT)
should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT
is logic 1. Note that when Timer 2 overflows are used as the conversion source, Low Byte overflows are
used if Timer2 is in 8-bit mode; High byte overflows are used if Timer 2 is in 16-bit mode. See Section
“18. Timers” on page 182 for timer configuration.
Important Note: The CNVSTR input pin also functions as Port pin P0.5 on C8051F52x/52xA devices and
P1.2 on C8051F53x/53xA devices. When the CNVSTR input is used as the ADC0 conversion source, Port
pin P0.5 or P1.2 should be skipped by the Digital Crossbar. To configure the Crossbar to skip P0.5 or P1.2,
set to 1 to the appropriate bit in the PnSKIP register. See Section “13. Port Input/Output” on page 120 for
details on Port I/O configuration.
4.3.2. Tracking Modes
Each ADC0 conversion must be preceded by a minimum tracking time for the converted result to be accu-
rate, as shown in Table 2.3 on page 28. ADC0 has three tracking modes: Pre-Tracking, Post-Tracking, and
Dual-Tracking. Pre-Tracking Mode provides the minimum delay between the convert start signal and end
of conversion by tracking continuously before the convert start signal. This mode requires software man-
agement in order to meet minimum tracking requirements. In Post-Tracking Mode, a programmable track-
ing time starts after the convert start signal and is managed by hardware. Dual-Tracking Mode maximizes
tracking time by tracking before and after the convert start signal. Figure 4.3 shows examples of the three
tracking modes.
Pre-Tracking Mode is selected when AD0TM is set to 10b. Conversions are started immediately following
the convert start signal. ADC0 is tracking continuously when not performing a conversion. Software must
allow at least the minimum tracking time between each end of conversion and the next convert start signal.
The minimum tracking time must also be met prior to the first convert start signal after ADC0 is enabled.
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C8051F531-C-IMR 制造商:Silicon Laboratories Inc 功能描述:25 MIPS, 8 KB, 256, SPI, UART, QFN20 - Tape and Reel 制造商:Silicon Laboratories Inc 功能描述:IC MCU 8051 8KB FLASH 20QFN
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