參數(shù)資料
型號(hào): C8051F332-GM
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 83/210頁(yè)
文件大小: 0K
描述: IC 8051 MCU 4KB FLASH 20QFN
產(chǎn)品培訓(xùn)模塊: Serial Communication Overview
標(biāo)準(zhǔn)包裝: 91
系列: C8051F33x
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SMBus(2 線/I²C),SPI,UART/USART
外圍設(shè)備: POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 17
程序存儲(chǔ)器容量: 4KB(4K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-VFQFN 裸露焊盤
包裝: 管件
產(chǎn)品目錄頁(yè)面: 623 (CN2011-ZH PDF)
配用: 336-1451-ND - ADAPTER PROGRAM TOOLSTICK F330
其它名稱: 336-1266
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Rev. 1.7
177
C8051F330/1/2/3/4/5
18. Timers
Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the
standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose
use. These timers can be used to measure time intervals, count external events and generate periodic
interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation.
Timer 2 and Timer 3 offer 16-bit and split 8-bit timer functionality with auto-reload
Timers 0 and 1 may be clocked by one of five sources, determined by the Timer Mode Select bits (T1M
T0M) and the Clock Scale bits (SCA1
SCA0). The Clock Scale bits define a pre-scaled clock from which
Timer 0 and/or Timer 1 may be clocked (See SFR Definition 18.3 for pre-scaled clock selection).
Timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. Timer 2 and
Timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
clock source divided by 8.
Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer
register is incremented on each high-to-low transition at the selected input pin (T0 or T1). Events with a fre-
quency of up to one-fourth the system clock frequency can be counted. The input signal need not be peri-
odic, but it should be held at a given level for at least two full system clock cycles to ensure the level is
properly sampled.
18.1. Timer 0 and Timer 1
Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1)
and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and
Timer 1 as well as indicate status. Timer 0 interrupts can be enabled by setting the ET0 bit in the IE regis-
setting the ET1 bit in the IE register (
Section 9.3.5). Both counter/timers operate in one of four primary
modes selected by setting the Mode Select bits T1M1
T0M0 in the Counter/Timer Mode register (TMOD).
Each timer can be configured independently. Each operating mode is described below.
18.1.1. Mode 0: 13-bit Counter/Timer
Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration
and operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same
manner as described for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions
TL0.4
TL0.0. The three upper bits of TL0 (TL0.7TL0.5) are indeterminate and should be masked out or
ignored when reading. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to
0x0000, the timer overflow flag TF0 (TCON.5) is set and an interrupt will occur if Timer 0 interrupts are
enabled.
Timer 0 and Timer 1 Modes:
Timer 2 Modes:
Timer 3 Modes:
13-bit counter/timer
16-bit timer with auto-reload
16-bit counter/timer
8-bit counter/timer with auto-
reload
Two 8-bit timers with auto-reload
Two 8-bit counter/timers (Timer 0
only)
相關(guān)PDF資料
PDF描述
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