參數(shù)資料
型號: C8051F305-GS
廠商: Silicon Laboratories Inc
文件頁數(shù): 56/178頁
文件大?。?/td> 0K
描述: IC 8051 MCU 2K FLASH 14-SOIC
產品培訓模塊: Serial Communication Overview
標準包裝: 56
系列: C8051F30x
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SMBus(2 線/I²C),UART/USART
外圍設備: POR,PWM,WDT
輸入/輸出數(shù): 8
程序存儲器容量: 2KB(2K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
包裝: 管件
產品目錄頁面: 622 (CN2011-ZH PDF)
配用: 336-1444-ND - ADAPTER PROGRAM TOOLSTICK F300
其它名稱: 336-1540-5
Rev. 2.9
149
C8051F300/1/2/3/4/5
SFR Definition 15.3.
Bit7:
UNUSED. Read = 0b, Write = don’t care.
Bit6:
T2MH: Timer 2 High Byte Clock Select
This bit selects the clock supplied to the Timer 2 high byte if Timer 2 is configured in split 8-
bit timer mode. T2MH is ignored if Timer 2 is in any other mode.
0: Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 high byte uses the system clock.
Bit5:
T2ML: Timer 2 Low Byte Clock Select
This bit selects the clock supplied to Timer 2. If Timer 2 is configured in split 8-bit timer
mode, this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 low byte uses the system clock.
Bit4:
T1M: Timer 1 Clock Select.
This select the clock source supplied to Timer 1. T1M is ignored when C/T1 is set to logic 1.
0: Timer 1 uses the clock defined by the prescale bits, SCA1–SCA0.
1: Timer 1 uses the system clock.
Bit3:
T0M: Timer 0 Clock Select.
This bit selects the clock source supplied to Timer 0. T0M is ignored when C/T0 is set to
logic 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits, SCA1–SCA0.
1: Counter/Timer 0 uses the system clock.
Bit2:
UNUSED. Read = 0b, Write = don’t care.
Bits1–0: SCA1–SCA0: Timer 0/1 Prescale Bits
These bits control the division of the clock supplied to Timer 0 and/or Timer 1 if configured
to use prescaled clock inputs.
R/W
Reset Value
T2MH
T2ML
T1M
T0M
SCA1
SCA0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x8E
SCA1
SCA0
Prescaled Clock
0
System clock divided by 12
0
1
System clock divided by 4
1
0
System clock divided by 48
1
External clock divided by 8
Note: External clock divided by 8 is synchronized with the
system clock, and the external clock must be less
than or equal to the system clock to operate in this
mode.
CKCON: Clock Control
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