參數(shù)資料
型號: C8051F015-TB
廠商: Silicon Laboratories Inc
文件頁數(shù): 14/171頁
文件大?。?/td> 0K
描述: BOARD PROTOTYPING W/C8051F015
標(biāo)準(zhǔn)包裝: 1
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 15.8. P1: Port1 Register
R/W
Reset Value
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
11111111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
0x90
Bits7-0: P1.[7:0]
(Write – Output appears on I/O pins per XBR0, XBR1, and XBR2 registers)
0: Logic Low Output.
1: Logic High Output (high-impedance if corresponding PRT1CF.n bit = 0)
(Read – Regardless of XBR0, XBR1, and XBR2 Register settings).
0: P1.n pin is logic low.
1: P1.n pin is logic high.
Figure 15.9. PRT1CF: Port1 Configuration Register
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xA5
Bits7-0: PRT1CF.[7:0]: Output Configuration Bits for P1.7-P1.0 (respectively)
0: Corresponding P1.n Output mode is Open-Drain.
1: Corresponding P1.n Output mode is Push-Pull.
Figure 15.10. PRT1IF: Port1 Interrupt Flag Register
R/W
Reset Value
IE7
IE6
IE5
IE4
-
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xAD
Bit7:
IE7: External Interrupt 7 Pending Flag.
0: No falling edge detected on P1.7.
1: This flag is set by hardware when a falling edge on P1.7 is detected.
Bit6:
IE6: External Interrupt 6 Pending Flag.
0: No falling edge detected on P1.6.
1: This flag is set by hardware when a falling edge on P1.6 is detected.
Bit5:
IE5: External Interrupt 5 Pending Flag.
0: No falling edge detected on P1.5.
1: This flag is set by hardware when a falling edge on P1.5 is detected.
Bit4:
IE4: External Interrupt 4 Pending Flag.
0: No falling edge detected on P1.4.
1: This flag is set by hardware when a falling edge on P1.4 is detected.
Bits3-0: UNUSED. Read = 0000b, Write = don’t care.
Rev. 1.7
110
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