參數(shù)資料
型號: C8051F010-TB
廠商: Silicon Laboratories Inc
文件頁數(shù): 54/171頁
文件大?。?/td> 0K
描述: BOARD PROTOTYPING W/C8051F010
標準包裝: 1
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
19.2.1. Mode 0: 16-bit Counter/Timer with Capture
In this mode, Timer 2 operates as a 16-bit counter/timer with capture facility. A high-to-low transition on the T2EX
input pin causes the 16-bit value in Timer 2 (TH2, TL2) to be loaded into the capture registers (RCAP2H,
RCAP2L).
Timer 2 can use either SYSCLK, SYSCLK divided by 12, or high-to-low transitions on the external T2 pin as its
clock source when operating in Counter/Timer with Capture mode. Clearing the C/T2 bit (T2CON.1) selects the
system clock as the input for the timer (divided by one or twelve as specified by the Timer Clock Select bit T2M in
CKCON). When C/T2 is set to logic 1, a high-to-low transition at the T2 input pin increments the counter/timer
register. As the 16-bit counter/timer register increments and overflows from 0xFFFF to 0x0000, the TF2 timer
overflow flag (T2CON.7) is set and an interrupt will occur if the interrupt is enabled.
Counter/Timer with Capture mode is selected by setting the Capture/Reload Select bit CP/RL2 (T2CON.0) and the
Timer 2 Run Control bit TR2 (T2CON.2) to logic 1. The Timer 2 External Enable EXEN2 (T2CON.3) must also be
set to logic 1 to enable a capture. If EXEN2 is cleared, transitions on T2EX will be ignored.
Figure 19.11. T2 Mode 0 Block Diagram
TL2
TH2
EXEN2
T2EX
TR2
T2
SYSCLK
12
0
1
0
Interrupt
TCLK
RCAP2L
RCAP2H
Capture
T2CO
N
RCLK
TCLK
EXF2
EXEN2
TR2
C/T2
CP/RL2
TF2
CKCON
T
2
M
T
1
M
T
0
M
Crossbar
147
Rev. 1.7
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