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| 型號(hào)： | C8051F010-TB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 160/171頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD PROTOTYPING W/C8051F010 |
| 標(biāo)準(zhǔn)包裝： | 1 |
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C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 11.2. Flash Program Memory Security Bytes
0x7E00
0x807F
0x8000
0x7DF
E
Program Memory
Space
0x0000
0x7DFF
Read Lock Byte
Write/Erase Lock Byte
Software Read Limit
Reserved
Bit
Memory Block
7
6
5
4
0x6000 - 0x6FFF
0x7000 - 0x7DFD
0x5000 - 0x5FFF
0x4000 - 0x4FFF
3
2
1
0
0x2000 - 0x2FFF
0x3000 - 0x3FFF
0x1000 - 0x1FFF
0x0000 - 0x0FFF
0x7FFF
Read and Write/Erase Security Bits.
(Bit 7 is MSB.)
(This Block locked only if all
other blocks are locked)
0x7DFD
The lock bits can always be read and cleared to logic 0 regardless of the security setting applied to the block
containing the security bytes. This allows additional blocks to be protected after the block containing the security
bytes has been locked. However, the only means of removing a lock once set is to erase the entire program memory
space by performing a JTAG erase operation (i.e. cannot be done in user firmware). NOTE: Addressing either
security byte while performing a JTAG erase operation will automatically initiate erasure of the entire
program memory space (except for the reserved area). This erasure can only be performed via JTAG. If a
non-security byte in the 0x7C00-0x7DFF page is addressed during erasure, only that page (including the
security bytes) will be erased.
FLASH Read Lock Byte
Bits7-0: Each bit locks a corresponding block of memory. (Bit 7 is MSB.)
0: Read operations are locked (disabled) for corresponding block across the JTAG interface.
1: Read operations are unlocked (enabled) for corresponding block across the JTAG interface.
FLASH Write/Erase Lock Byte
Bits7-0: Each bit locks a corresponding block of memory.
0: Write/Erase operations are locked (disabled) for corresponding block across the JTAG interface.
1: Write/Erase operations are unlocked (enabled) for corresponding block across the JTAG interface.
FLASH Access Limit Register (FLACL)
The content of this register is used as the high byte of the 16-bit software read limit address. The 16-
bit read limit address value is calculated as 0xNN00 where NN is replaced by the contents of this
register. Software running at or above this address is prohibited from using the MOVX or MOVC
instructions to read, write, or erase, locations below this address. Any attempts to read locations
below this limit will return the value 0x00.
The Flash Access Limit security feature (see Figure 11.3) protects proprietary program code and data from being
read by software running on the C8051F005/06/07/15/16/17 MCUs. This feature provides support for OEMs that
wish to program the MCU with proprietary value-added firmware before distribution. The value-added firmware
can be protected while allowing additional code to be programmed in remaining program memory space later.
The Software Read Limit (SRL) is a 16-bit address that establishes two logical partitions in the program memory
space. The first is an upper partition consisting of all the program memory locations at or above the SRL address,
and the second is a lower partition consisting of all the program memory locations starting at 0x0000 up to (but
excluding) the SRL address.
Software in the upper partition can execute code in the lower partition, but is
89
Rev. 1.7
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| C8051F011 | 功能描述:8位微控制器 -MCU 32KB 10ADC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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| C8051F011R | 功能描述:8位微控制器 -MCU C 10Bit 48Pin RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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