參數(shù)資料
型號： C8051F000
廠商： Silicon Laboratories Inc
文件頁數(shù)： 44/171頁
文件大?。?/td> 0K
描述： IC 8051 MCU 32K FLASH 64TQFP
標(biāo)準(zhǔn)包裝： 160
系列： C8051F00x
核心處理器： 8051
芯體尺寸： 8-位
速度： 20MHz
連通性： SMBus（2 線/I²C），SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TQFP
包裝： 托盤
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
19. TIMERS
Each MCU implements four counter/timers: three are 16-bit counter/timers compatible with those found in the
standard 8051, and one is a 16-bit timer for use with the ADC, SMBus, or for general purpose use. These can be
used to measure time intervals, count external events and generate periodic interrupt requests. Timer 0 and Timer 1
are nearly identical and have four primary modes of operation. Timer 2 offers additional capabilities not available
in Timers 0 and 1. Timer 3 is similar to Timer 2, but without the capture or Baud Rate Generator modes.
Timer 0 and Timer 1:
Timer 2:
Timer 3:
13-bit counter/timer
16-bit counter/timer with auto-reload
16-bit timer with auto-reload
16-bit counter/timer
16-bit counter/timer with capture
8-bit counter/timer with auto-reload
Baud rate generator
Two 8-bit counter/timers (Timer 0 only)
When functioning as a timer, the counter/timer registers are incremented on each clock tick. Clock ticks are derived
from the system clock divided by either one or twelve as specified by the Timer Clock Select bits (T2M-T0M) in
CKCON. The twelve-clocks-per-tick option provides compatibility with the older generation of the 8051 family.
Applications that require a faster timer can use the one-clock-per-tick option.
When functioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected
input pin for T0, T1, or T2. Events with a frequency of up to one-fourth the system clock’s frequency can be
counted. The input signal need not be periodic, but it should be held at a given level for at least two full system
clock cycles to ensure the level is sampled.
19.1.
Timer 0 and Timer 1
Timer 0 and Timer 1 are accessed and controlled through SFRs. Each counter/timer is implemented as a 16-bit
register accessed as two separate bytes: a low byte (TL0 or TL1) and a high byte (TH0 or TH1).
The
Counter/Timer Control (TCON) register is used to enable Timer 0 and Timer 1 as well as indicate their status. Both
counter/timers operate in one of four primary modes selected by setting the Mode Select bits M1-M0 in the
Counter/Timer Mode (TMOD) register. Each timer can be configured independently. Following is a detailed
description of each operating mode.
19.1.1. Mode 0: 13-bit Counter/Timer
Timer 0 and Timer 1 operate as a 13-bit counter/timer in Mode 0. The following describes the configuration and
operation of Timer 0. However, both timers operate identically and Timer 1 is configured in the same manner as
described for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions TL0.4-
TL0.0. The three upper bits of TL0 (TL0.7-TL0.5) are indeterminate and should be masked out or ignored when
reading.
As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to 0x0000, the timer
overflow flag TF0 (TCON.5) is set and an interrupt will occur if enabled.
The C/T0 bit (TMOD.2) selects the counter/timer’s clock source. Clearing C/T selects the system clock as the input
for the timer. When C/T0 is set to logic 1, high-to-low transitions at the selected input pin increment the timer
register. (Refer to Port I/O Section 15.1 for information on selecting and configuring external I/O pins.)
Rev. 1.7
138
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