參數(shù)資料
型號: C8051F000-TB
廠商: Silicon Laboratories Inc
文件頁數(shù): 65/171頁
文件大?。?/td> 0K
描述: BOARD PROTOTYPING W/C8051F000
標(biāo)準(zhǔn)包裝: 1
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
20.1.2. Software Timer (Compare) Mode
In Software Timer mode, the PCA counter/timer is compared to the module’s 16-bit capture/compare register
(PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to
logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn bit is not automatically
cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software.
Setting the ECOMn and MATn bits in the PCA0CPMn register enables Software Timer mode.
Figure 20.4. PCA Software Timer Mode Diagram
Match
16-bit Comparator
PCA0H
PCA0CPHn
Enable
PCA0L
PCA
Timebase
PCA0CPLn
PCA0CPMn
E
C
O
M
n
E
C
F
n
T
O
G
n
P
W
M
n
C
A
P
n
C
A
P
N
n
M
A
T
n
00
PCA0CN
C
F
C
R
C
F
0
C
F
2
C
F
1
C
F
4
C
F
3
PCA Interrupt
0
1
x
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
20.1.3. High Speed Output Mode
In this mode, each time a match occurs between the PCA Timer Counter and a module’s 16-bit capture/compare
register (PCA0CPHn and PCA0CPLn) the logic level on the module’s associated CEXn pin will toggle. Setting the
TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High-Speed Output mode.
Figure 20.5. PCA High Speed Output Mode Diagram
Match
16-bit Comparator
PCA0H
PCA0CPHn
Enable
PCA0L
PCA
Timebase
PCA0CPLn
PCA0CN
C
F
C
R
C
F
0
C
F
2
C
F
1
C
F
4
C
F
3
PCA Interrupt
0
1
PCA0CPMn
E
C
O
M
n
E
C
F
n
T
O
G
n
P
W
M
n
C
A
P
n
C
A
P
N
n
M
A
T
n
00
0 x
CEXn
Crossbar
Port I/O
Toggle
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
0
1
TOGn
157
Rev. 1.7
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