參數(shù)資料
型號： C8051F000-TB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 37/171頁
文件大小： 0K
描述： BOARD PROTOTYPING W/C8051F000
標準包裝： 1
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
18.1.
UART Operational Modes
The UART provides four operating modes (one synchronous and three asynchronous) selected by setting
configuration bits in the SCON register. These four modes offer different baud rates and communication protocols.
The four modes are summarized in Table 18.1 below. Detailed descriptions follow.
Table 18.1. UART Modes
Mode
Synchronization
Baud Clock
Data Bits
Start/Stop Bits
0
Synchronous
SYSCLK/12
8
None
1
Asynchronous
Timer 1 or Timer 2 Overflow
8
1 Start, 1 Stop
2
Asynchronous
SYSCLK/32 or SYSCLK/64
9
1 Start, 1 Stop
3
Asynchronous
Timer 1 or Timer 2 Overflow
9
1 Start, 1 Stop
18.1.1. Mode 0: Synchronous Mode
Mode 0 provides synchronous, half-duplex communication. Serial data is transmitted and received on the RX pin.
The TX pin provides the shift clock for both transmit and receive. The MCU must be the master since it generates
the shift clock for transmission in both directions (see the interconnect diagram in Figure 18.2).
Eight data bits are transmitted/received, LSB first (see the timing diagram in Figure 18.3). Data transmission begins
when an instruction writes a data byte to the SBUF register. The TI Transmit Interrupt Flag (SCON.1) is set at the
end of the eighth bit time. Data reception begins when the REN Receive Enable bit (SCON.4) is set to logic 1 and
the RI Receive Interrupt Flag (SCON.0) is cleared. One cycle after the eighth bit is shifted in, the RI flag is set and
reception stops until software clears the RI bit. An interrupt will occur if enabled when either TI or RI is set.
The Mode 0 baud rate is the system clock frequency divided by twelve. RX is forced to open-drain in mode 0, and
an external pull-up will typically be required.
Figure 18.2. UART Mode 0 Interconnect
Shift
Reg.
CLK
C8051Fxxx
RX
TX
DATA
8 Extra Outputs
Figure 18.3. UART Mode 0 Timing Diagram
18.1.2. Mode 1: 8-Bit UART, Variable Baud Rate
D1
D0
D2
D3
D4
D5
D6
D7
RX (data out)
MODE 0 TRANSMIT
D0
MODE 0 RECEIVE
RX (data in)
D1
D2
D3
D4
D5
D6
D7
TX (clk out)
131
Rev. 1.7
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