
These designs face a number of
limitations:
Frame processing is limited by the
CPU performance. A generous esti-
mate of top-end performance for
Frame Relay or IP is up to 350,000
frames per second (though typically far
worse), which is approximately one-
third of wire-speed performance for
one DS3 (assuming 8-byte Frame
Relay frames).
Density is limited by processing perfor-
mance, PCI bandwidth, and compo-
nent board space. A generous best-
case design might support up to five
DS3s.
System cost is driven by the ASSP
costs, with complex HDLC controllers
and OC-12 SARs typically costing hun-
dreds of dollars for each part.
The C-5 NP breaks through these limita-
tions by integrating these functions into
a single chip. Channel Processors are
dedicated to ATM, SAR, HDLC multiplex-
ing and demultiplexing, Frame Relay,
and IP functions, enabling wire-speed
operations.
The C-5 NP implementation offers clear
benefits:
Density of up to 10 DS3s is easily
achieved, enabled by the processing
power, internal bandwidth, and integra-
tion of a single C-5 NP
Wire-speed performance can be
achieved even for 10 individual DS3
links (over 7 million frames per sec-
ond), delivering over 20 times the per-
formance of general-purpose CPU-
based designs.
System costs are dramatically
reduced, both through integration
of multiple, expensive components
and provision of much higher port
densities.
The same hardware and software
architecture scales to higher speeds,
up to OC-48, enabling extensive lever-
age across the product line for
improved time-to-market and lower
support costs.
6XPPDU\
The C-5 NP is a revolutionary break-
through for networking vendors and their
customers. Its unique combinExecutive
complete programmability and wire-
speed performance provides the best
foundation for building value-added
networking products and servFabric
the 21
st
century.
Internal Bandwidth
Memory
Memory
T-Carrier
Framers
x N
T-Carrier
Framers
ATM
Port
HDLC
Controller
HDLC
Controller
AAL5 SAR
AAL5 SAR
System
Control
Throughput
CPU
Memory
Memory
Concurrent
Network Processing
ATM Interworking with Costly Multi-part Design
)HDWXUH
P
C-5 NP
Physical Interfaces
PCI Bus to
Host Processor
T-Carrier
Framers
x N
T-Carrier
Framers
ATM
Port
HDLC CP
Processor (CP)
HDLC CP
TLU/QMU/
BMU
6
AAL5 SAR
CPs
Fabric
Processor
FRF/ATM
IP CPs
Executive
Processor
Memories
ATM Interworking with the C-5 NP
)XQFWLRQ
C-5 NP
General
16 Channel Processors for cell/packet
processing
tasks:
- Executive Processor (supervisory tasks)
- Fabric Processor (high-speed fabric
interface management)
- Table Lookup Unit (networking lookups)
- Queue Management Unit (queue control)
- Buffer Management Unit (payload storage)
5Gbps aggregate
Three internal buses with 60Gbps aggregate
bandwidth
Over 3000 MIPS
Layout
Single Chip System
Ball Grid Array (BGA) package
Up to 16 (user configurable)
10Mb Ethernet (RMII)
100Mb Ethernet (RMII)
1Gb Ethernet (GMII and TBI)
OC-3c
OC-12/OC-12c
OC-48
FibreChannel
T1/E1 (with external framers/multiplexors)
T3/E3 (with external framers/multiplexors)
RISC Core
32-bit C/C++ programmable, standard
instruction set
Programmable
Serial Data
Processors (SDPs)
Two SDPs (one receive and one transmit) per
CP
Processor (XP)
RISC Core
C/C++ programmable, standard instruction
set
External Interfaces
32-bit, 33/66MHz PCI
Serial PROM interface
Two-wire serial bus interface (400kbps)
Processor (FP)
Interface Type
Conforms to UTOPIA (Levels 2 and 3)
interface standards, and seamless
compatibility with Power X and IBM fabrics
Interface
Bandwidth
Transmit and receive full-duplex at up to
3200Mbps each direction
Table Lookup
Unit (TLU)
Number of Lookups
per Second
133M maximum
External Memory
Size
Up to 16MB maximum (8Mb x 18)
Queue
Management
Unit (QMU)
Internal Mode
Up to 512 queues
Automated multicast elaboration
Buffer
Management
Unit (BMU)
Buffer Memory
Width
139 bit (128 bits data, 9 bits ECC, 2 bits
control)
Buffer Memory Size Up to 128MB
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.