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| 型號(hào)： | C5NP-PB |
| 英文描述： | ANALOG MULTIPLEXER/DEMULTIPLEXER |
| 中文描述： | 的C - 5網(wǎng)絡(luò)處理器概況 |
| 文件頁(yè)數(shù)： | 2/4頁(yè) |
| 文件大小： | 683K |
| 代理商： | C5NP-PB |
Network I/O
5Gbps
Host I/O
2Gbps
Internal
I/O
60Gbps
Fabric I/O
5Gbps
CP0
CP1
CP15
XP
FP
TLU
QMU BMU
SRAM or
Ext. QM
SDRAM
18 integrated processors
available for value-added
Networking Intelligence
3 optimized coprocessors offload
specialized networking tasks that
are common across applications
C-5 NP
High Functional Integration
SRAM or
Ext. TLE
PHY
PHY
PHY
PHY
C-5 NP
C-5 NP
C-5 NP
PHY
C-5 NP
C-5 NP
Fabric
System Scaling
CSIX standard
Custom interconnects
Glueless fabric alliances
Physical Layer
(DS1 to OC-48 rates)
T/E-Carrier, Ethernet, POS,
ATM, SONET, FR, DWDM,
FibreChannel, ...
5Gbps
Aggregate
Bandwidth
10Gbps
Aggregate
Bandwidth
Terabits of
Aggregate
Bandwidth
Network
Intelligence
Traffic classification
Policy management
VPN and MPLS services
Quality of Service
Switching/Routing
Interworking, ...
Scalable Network Intelligence
and tomorrow’s demanding communica-
tions requirements. The C-5 NP’s 5Gbps
of bandwidth gives you non-blocking
throughput and the 3,000 MIPs of com-
puting power allows you to add services
throughout the protocol stack
—
all at
wire-speed.
You can use more than one C-5 NP per
device to increase both your bandwidth
and computing power. In addition, multi-
ple C-5 NPs can be used in conjunction
with a switching fabric to implement
large scale switching systems. With two
C-5 NPs, you can scale your system up to
10Gbps aggregate bandwidth. By adding
multiple C-5 NPs and a fabric interface,
you can achieve Terabits per second of
aggregate band-
width.
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The C-5 NP’s highly
tions building blocks that can be
integrated architec-
customized through standard software
ture employs dedi-
and that enable more than three billion
cated processors for
RISC cycles per second to be used for
value-added net-
working ivalue-added serviprocessing power, bandwidth, through-
processing is pipelined using special-
and a series of
coprocessors that
off-load many com-
mon networking-specific tasSpecific forwarding functions supporting
architecture allows the procedifferent wire-speed network interfaces,
coprocessors to support conline speeds, and protocols are imple-
cessing, which helps the C-5 mented using the C/C++ programmable
deliver software flexibility at RISC Core. The RISC Core specifically
speeds.
The C-5 NP’s sixteen progra Characterization and classification
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are r Policy enforcement
for receiving, processing, an Traffic scheduling
ting cells and packets. The C-The programmable SDPs handle com-
coprocessors operate as sharmon, time-consuming tasks such as:
resources for the CPs and each other and
perform a range of networking-tion (including header validation), inser-
tasks. The coprocessors are:
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the C-5 NP and coordinating the
C-5 NP and external processors
for Framing and encoding/decoding
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scaling the C-5 NP with
industry leading fabrics
for
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implementing complex
table searches and
updates
for
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for integrating
queue control and man-
agement
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for providing fast,
flexible memory manage-
ment
Three independent data buses provide
Each Channel Pro60Gbps internal communication paths
RISC Core plus dbetween the processors and The C-5 NP’s architecture
The Channel Processors (CPs) can be
combined in several ways to system development, simplify
put, or all three. Typically one CP is
assigned to each port for medium band-
width applications (Fast EtheThe physical interfaces of the C-5
OC-3). Note that a single CP NP are programmed on a per port
full duplex wire-speed procesbasis, enabling a single C-5 NP to
Channel Processor
RISC Core
ters for wider data streams while still
Extract
Space
Space
Data
model. Both techniques can be appliSimilar to APIs in the computing
simultaneously and are supported by
sophisticated hardware mechanisms,
minimizing the complexity of softwaNP and abstract the most com-
development.
Single CP Application
CP Parallel Processing
CP Pipelined Processing
CP0
CP1
CP2
CP0
CP3
CP0
CP1
CPn
Parallel and Pipelined
Processing
Processors (SDPssors, further supporting concsupports a variety of industry-
ponents act as poprocessing.
purpose memories that loosely couple
these processors.
manages:
Programmable field parsing, extrac-
tion, and deletion
CRC validation/calculation
standard serial and parallel proto-
cols and individual port data rates
from DS1 (1.544Mbps) to OC-48.
Integrated functions including
MACs and SONET Framers speed
device design, and lower total
system costs.
simultaneously support a wide variety
of physical interface types.
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The C-5 NP is programmed using stan-
dard C/C++ languages rather than con-
figurable state-machines or proprietary
languages,
thus providing a true and sim-
ple programming model. In addition, the
C-5 NP’s standard RISC instruction set
enhances code portability and enables
use of standard development tools.
The key to a simple programming model,
however, is an open set of standard pro-
gramming interfaces. C-Port’s
C-Ware Applications Program-
ming Interfaces (C-Ware APIs)
simplify communications soft-
ware development and efficiently
leverage the power of the C-5 NP
world, the C-Ware APIs hide the
sophisticated hardware of the C-5
mon network task building
blocks, such as physical interface
management, data forwarding, table
lookups, buffer management, queuing
operations, and so on. Programming to
the C-Ware APIs ensures software com-
patibility and scalability from generation
to generation of the C-Port family of
network processors.
Control
Table
Merge
Serial Data
Processor
(Receive)
Processor
(Transmit)
Memory
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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