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C508
Data Sheet
52
2000-08
The Watchdog Timer can be started by software (bit SWDT in SFR IEN1), but it cannot
be stopped during active mode of the device. If the software fails to clear the Watchdog
Timer an internal reset will be initiated. The cause of the reset (either an external reset
or a reset caused by the watchdog) can be examined by software (status flag WDTS in
IP0 is set). A refresh of the Watchdog Timer is done by setting bits WDT (SFR IEN0) and
SWDT consecutively. This double instruction sequence has been implemented to
increase system security. It must be noted, however, that the Watchdog Timer is halted
during the idle mode and power-down mode of the processor.
Table 11
WDTREL
Oscillator Watchdog Unit
The Oscillator Watchdog unit serves for three functions:
Monitoring of the on-chip oscillator’s function
The watchdog supervises the on-chip oscillator’s frequency; if it is lower than the
frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is
supplied by the RC oscillator and the device is brought into reset. If the failure
condition disappears (i.e. the on-chip oscillator has a higher frequency than the RC
oscillator), the part executes a final reset phase of typically 1 ms in order to allow the
oscillator to stabilize; then, the Oscillator Watchdog reset is released and the part
starts program execution again.
Fast internal reset after power-on
The Oscillator Watchdog unit provides a clock supply for the reset before the on-chip
oscillator and the PLL have started.
Control of external wake-up from software power-down mode
When the software power-down mode is terminated by a low level at pins P3.2/INT0
or P5.7/INT7, the Oscillator Watchdog unit ensures that the microcontroller resumes
operation (execution of the power-down wake-up interrupt) with the nominal clock
rate. In the power-down mode the RC oscillator, the on-chip oscillator and the PLL are
stopped. They are started again when power-down mode is terminated. After the on-
chip oscillator is stable and the PLL has been locked, the microcontroller starts
program execution.
Note: The Oscillator Watchdog unit is always enabled.
Watchdog Timer Time-Out Periods
Time-Out Period
f
OSC
= 5 MHz
f
OSC
= 8 MHz
39.322 ms
24.576 ms
629.146 ms
393.2 ms
307.2
μ
s
192
μ
s
Comments
f
OSC
= 10 MHz
19.668 ms
314.573 ms
153.6
μ
s
00
H
80
H
7F
H
This is the default value
Maximum time period
Minimum time period