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參數(shù)資料
| 型號(hào)： | C505-2RM |
| 廠(chǎng)商： | SIEMENS AG |
| 元件分類(lèi)： | 8位微控制器 |
| 英文描述： | 8-Bit CMOS Microcontroller |
| 中文描述： | 8位CMOS微控制器 |
| 文件頁(yè)數(shù)： | 57/85頁(yè) |
| 文件大小： | 335K |
| 代理商： | C505-2RM |
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Semiconductor Group
57
1997-12-01
C505 / C505C
C505A / C505CA
Lock Bits Programming / Read
The C505A/C505CA has two programmable lock bits which, when programmed according
table 14
,
provide four levels of protection for the on-chip OTP code memory. The state of the lock bits can
also be read.
Table 13
Access Modes Selection
Access Mode
EA/
V
PP
PROG
PRD
PMSEL
Address
(Port 2)
Data
(Port 0)
1
0
Program OTP memory byte
V
PP
V
IH
V
PP
V
IH
V
IH
H
H
H
A0-7
A8-14
D0-7
Read OTP memory byte
H
Program OTP lock bits
H
H
L
–
D1,D0 see
table 14
Read OTP lock bits
H
Read OTP version byte
H
L
H
Byte addr.
of version
byte
D0-7
Table 14
Lock Bit Protection Types
Lock Bits at D1,D0
Protection
Level
Protection Type
D1
D0
1
1
Level 0
The OTP lock feature is disabled. During normal operation of
the C505A/C505CA, the state of the EA pin is not latched on
reset.
1
0
Level 1
During normal operation of the C505A/C505CA, MOVC
instructions executed from external program memory are
disabled from fetching code bytes from internal memory. EA is
sampled and latched on reset. An OTP memory read operation
is only possible using the ROM/OTP verification mode 2 for
protection level 1. Further programming of the OTP memory is
disabled (reprogramming security).
0
1
Level 2
Same as level 1, but also OTP memory read operation using
OTP verification mode is disabled.
0
0
Level 3
Same as level 2; but additionally external code execution by
setting EA=low during normal operation of the C505A/C505CA
is no more possible.
External code execution, which is initiated by an internal
program (e.g. by an internal jump instruction above the ROM
boundary), is still possible.
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