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參數(shù)資料
| 型號： | C505-2RM |
| 廠商： | SIEMENS AG |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-Bit CMOS Microcontroller |
| 中文描述： | 8位CMOS微控制器 |
| 文件頁數(shù)： | 38/85頁 |
| 文件大?。?/td> | 335K |
| 代理商： | C505-2RM |
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Semiconductor Group
38
1997-12-01
C505 / C505C
C505A / C505CA
The
TX/RX
Shift Register
holds the destuffed bit stream from the bus line to allow the parallel
access to the whole data or remote frame for the acceptance match test and the parallel transfer of
the frame to and from the Intelligent Memory.
The
Bit Stream Processor (BSP)
is a sequencer controlling the sequential data stream between
the TX/RX Shift Register, the CRC Register, and the bus line. The BSP also controls the EML and
the parallel data stream between the TX/RX Shift Register and the Intelligent Memory such that the
processes of reception, arbitration, transmission, and error signalling are performed according to
the CAN protocol. Note that the automatic retransmission of messages which have been corrupted
by noise or other external error conditions on the bus line is handled by the BSP.
The
Cyclic Redundancy Check Register (CRC)
generates the Cyclic Redundancy Check code to
be transmitted after the data bytes and checks the CRC code of incoming messages. This is done
by dividing the data stream by the code generator polynomial.
The
Error Management Logic (EML)
is responsible for the fault confinement of the CAN device. Its
counters, the Receive Error Counter and the Transmit Error Counter, are incremented and
decremented by commands from the Bit Stream Processor. According to the values of the error
counters, the CAN controller is set into the states error active error passiveand busoff.
The
Bit Timing Logic (BTL)
monitors the busline input RXDC and handles the busline related bit
timing according to the CAN protocol. The BTL synchronizes on a recessiveto dominantbusline
transition at Start of Frame(hard synchronization) and on any further recessiveto dominantbusline
transition, if the CAN controller itself does not transmit a dominantbit (resynchronization). The BTL
also provides programmable time segments to compensate for the propagation delay time and for
phase shifts and to define the position of the Sample Point in the bit time. The programming of the
BTL depends on the baudrate and on external physical delay times.
The
Intelligent Memory
(CAM/RAM array) provides storage for up to 15 message objects of
maximum 8 data bytes length. Each of these objects has a unique identifier and its own set of
control and status bits. After the initial configuration, the Intelligent Memory can handle the
reception and transmission of data without further microcontroller actions.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| C505C-2RM | 8-Bit CMOS Microcontroller |
| C505-LM | 8-Bit CMOS Microcontroller |
| C505A-4EM | 8-Bit CMOS Microcontroller |
| C505C-LM | 8-Bit CMOS Microcontroller |
| C505CA-2R | 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| C5056 | 制造商:TE Connectivity 功能描述:TRANSFORMER - Tape and Reel |
| C5057 | 制造商:TE Connectivity 功能描述:TRANSFORMER - Tape and Reel |
| C5058 | 制造商:TE Connectivity 功能描述:TRANSFORMER - Tape and Reel |
| C505A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit Single-Chip Microcontroller |
| C505A-2R | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit Single-Chip Microcontroller |
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