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| 型號： | C161S |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 16-Bit Single-Chip Microcontroller |
| 中文描述： | 16位單片機 |
| 文件頁數(shù)： | 48/75頁 |
| 文件大小： | 1315K |
| 代理商： | C161S |
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C161S
Timing Characteristics
Data Sheet
44
V1.0, 2003-11
5
Timing Characteristics
5.1
Definition of Internal Timing
The internal operation of the C161S is controlled by the internal CPU clock
f
CPU
. Both
edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)
operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called
“
TCL
”
(see
Figure 10
).
Figure 10
Generation Mechanisms for the CPU Clock
The CPU clock signal
f
CPU
can be generated from the oscillator clock signal
f
OSC
via
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate
f
CPU
. This influence must
be regarded when calculating the timings for the C161S.
Note: The example for PLL operation shown in
Figure 10
refers to a PLL factor of 4.
The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5. Upon a long hardware reset register RP0H is loaded with the logic
MCT04338
f
OSC
f
CPU
Phase Locked Loop Operation
TCL
f
OSC
f
CPU
Direct Clock Drive
f
OSC
f
CPU
Prescaler Operation
TCL
TCL
TCL
TCL
TCL
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