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參數(shù)資料
| 型號： | C161S |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 16-Bit Single-Chip Microcontroller |
| 中文描述： | 16位單片機 |
| 文件頁數(shù)： | 10/75頁 |
| 文件大?。?/td> | 1315K |
| 代理商： | C161S |
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C161S
General Device Information
Data Sheet
6
V1.0, 2003-11
RD
25
O
External Memory Read Strobe. RD is activated for every
external instruction or data read access.
External Memory Write Strobe. In WR-mode this pin is
activated for every external data write access. In WRL-mode
this pin is activated for low byte data write accesses on a
16-bit bus, and for every data write access on an 8-bit bus.
See WRCFG in register SYSCON for mode selection.
Address Latch Enable Output. Can be used for latching the
address into external memory or an address latch in the
multiplexed bus modes.
External Access Enable pin. A low level at this pin during and
after Reset forces the C161S to begin instruction execution
out of external memory. A high level forces execution out of
the internal program memory.
“ROMless” versions must have this pin tied to ‘0’.
PORT0 consists of the two 8-bit bidirectional I/O ports P0L
and P0H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state.
In case of an external bus configuration, PORT0 serves as
the address (A) and address/data (AD) bus in multiplexed
bus modes and as the data (D) bus in demultiplexed bus
modes.
Demultiplexed bus modes:
Data Path Width:
8-bit
P0L.0 – P0L.7:
D0 – D7
P0H.0 – P0H.7:
I/O
Multiplexed bus modes:
Data Path Width:
8-bit
P0L.0 – P0L.7:
AD0 – AD7
P0H.0 – P0H.7:
A8 – A15
WR/
WRL
26
O
ALE
27
O
EA
28
I
PORT0
P0L.0-7
P0H.0-7
29-36
39-46
IO
16-bit
D0 – D7
D8 – D15
16-bit
AD0 – AD7
AD8 – AD15
Table 2
Symbol
Pin Definitions and Functions
(cont’d)
Pin
No.
Outp.
Input
Function
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