參數(shù)資料
型號(hào): C161RI
廠商: SIEMENS AG
英文描述: 16-Bit CMOS Single-Chip Microcontroller
中文描述: 16位CMOS單芯片微控制器
文件頁(yè)數(shù): 7/60頁(yè)
文件大?。?/td> 614K
代理商: C161RI
Semiconductor Group
7
1998-05-01
C161RI
Pin Definitions and Functions
Symbol
Pin No.
TQFP
Pin No.
MQFP
Input
Outp
Function
P5.0 –
P5.3,
P5.14 –
P5.15
97 –
100,
1 –
2
99 –
2,
3 –
4
I
I
I
I
Port 5 is a 6-bit input-only port with Schmitt-Trigger
characteristics. The pins of Port 5 also serve as the (up to 4)
analog input channels for the A/D converter, where P5.x
equals ANx (Analog input channel x, x=0...3).
The following pins of Port 5 also serve as timer inputs:
P5.14
T4EUD
GPT1 Timer T4 Ext.Up/Down Ctrl.Input
P5.15
T2EUD
GPT1 Timer T5 Ext.Up/Down Ctrl.Input
XTAL1
XTAL2
4
5
6
7
I
O
XTAL1:
Input to the oscillator amplifier and input to the
internal clock generator
Output of the oscillator amplifier circuit.
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low
and
rise/fall
times
Characteristics must be observed.
XTAL2:
specified
in
the
AC
P3.0 –
P3.13,
P3.15
7 –
20,
21
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
9 –
22,
23
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
I/O
I/O
I/O
I/O
I/O
I
O
I
I
I
I
I/O
I/O
O
I/O
O
O
I/O
O
Port 3 is a 15-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state.
The following Port 3 pins also serve for alternate functions:
P3.0
SCL0
I
2
C Bus Clock Line 0
P3.1
SDA0
I
2
C Bus Data Line 0
P3.2
CAPIN
GPT2 Register CAPREL Capture Input
P3.3
T3OUT
GPT1 Timer T3 Toggle Latch Output
P3.4
T3EUD
GPT1 Timer T3 Ext.Up/Dwn Ctrl.Input
P3.5
T4IN
GPT1 Timer T4 Input for
Count/Gate/Reload/Capture
P3.6
T3IN
GPT1 Timer T3 Count/Gate Input
P3.7
T2IN
GPT1 Timer T2 Input for
Count/Gate/Reload/Capture
P3.8
MRST
SSC Master-Rec./Slave-Transmit I/O
P3.9
MTSR
SSC Master-Transmit/Slave-Rec. O/I
P3.10
T
×
D0
ASC0 Clock/Data Output (Asyn./Syn.)
P3.11
R
×
D0
ASC0 Data Input (Asyn.) or I/O (Syn.)
P3.12
BHE
Ext. Memory High Byte Enable Signal,
WRH
Ext. Memory High Byte Write Strobe
P3.13
SCLK
SSC Master Clock Outp./Slave Cl. Inp.
P3.15
CLKOUT
System Clock Output (=CPU Clock)
Note
:
Pins P3.0 and P3.1 are open drain outputs only.
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