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| 型號： | BXM80536GC1800F |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1800 MHz, MICROPROCESSOR, CPGA478 |
| 封裝： | FLIP CHIP, PGA-478 |
| 文件頁數(shù)： | 73/84頁 |
| 文件大?。?/td> | 1488K |
| 代理商： | BXM80536GC1800F |
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Package Mechanical Specifications and Pin Information
Datasheet
75
RS[2:0]#
Input
RS[2:0]# (Response Status) are driven by the response agent (the agent
responsible for completion of the current transaction), and must connect the
appropriate pins of both FSB agents.
RSVD
Reserved/
No
Connect
These pins are RESERVED and must be left unconnected on the board.
However, it is recommended that routing channels to these pins on the board be
kept open for possible future use. Please refer to the platform design guides for
more details.
SLP#
Input
SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter
the Sleep state. During Sleep state, the processor stops providing internal clock
signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts. The processor
will recognize only assertion of the RESET# signal, deassertion of SLP#, and
removal of the BCLK input while in Sleep state. If SLP# is deasserted, the
processor exits Sleep state and returns to Stop-Grant state, restarting its internal
clock signals to the bus and processor core units. If DPSLP# is asserted while in
the Sleep state, the processor will exit the Sleep state and transition to the Deep
Sleep state.
SMI#
Input
SMI# (System Management Interrupt) is asserted asynchronously by system
logic. On accepting a System Management Interrupt, the processor saves the
current state and enter System Management mode (SMM). An SMI
Acknowledge transaction is issued, and the processor begins program execution
from the SMM handler.
If SMI# is asserted during the deassertion of RESET# the processor will tristate
its outputs.
STPCLK#
Input
STPCLK# (Stop Clock), when asserted, causes the processor to enter a low
power Stop-Grant state. The processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core units
except the FSB and APIC units. The processor continues to snoop bus
transactions and service interrupts while in Stop-Grant state. When STPCLK# is
deasserted, the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK#
is an asynchronous input.
TCK
Input
TCK (Test Clock) provides the clock input for the processor test bus (also known
as the Test Access Port).
Please refer to the platform design guides for termination requirements and
implementation details.
TDI
Input
TDI (Test Data In) transfers serial test data into the processor. TDI provides the
serial input needed for JTAG specification support.
Please refer to the platform design guides for termination requirements and
implementation details.
TDO
Output
TDO (Test Data Out) transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
Please refer to the platform design guides for termination requirements and
implementation details.
TEST1,
TEST2
Input
TEST1 and TEST2 must have a stuffing option of separate pull down resistors to
VSS. Please refer to the platform design guides for more details.
THERMDA
Other
Thermal Diode Anode.
THERMDC
Other
Thermal Diode Cathode.
THERMTRIP#
Output
The processor protects itself from catastrophic overheating by use of an internal
thermal sensor. This sensor is set well above the normal operating temperature
to ensure that there are no false trips. The processor will stop all execution when
the junction temperature exceeds approximately 125 °C. This is signalled to the
system by the THERMTRIP# (Thermal Trip) pin.
For termination requirements please refer to the platform design guides .
Table 4-5. Signal Description (Sheet 6 of 7)
Name
Type
Description
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