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| 型號(hào)： | BXM80526B450256 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 450 MHz, MICROPROCESSOR, CPGA495 |
| 封裝： | MICRO PGA-495 |
| 文件頁(yè)數(shù)： | 74/84頁(yè) |
| 文件大小： | 450K |
| 代理商： | BXM80526B450256 |
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Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet
Intel Corporation
68
SMI# (I - 1.5V Tolerant)
The SMI# (System Management Interrupt) is asserted asynchronously by system logic. On
accepting a System Management Interrupt, the processor saves the current state and enters System
Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins
program execution from the SMM handler.
STPCLK# (I - 1.5V Tolerant)
The STPCLK# (Stop Clock) signal, when asserted, causes the processor to enter a low-power Stop
Grant state. The processor issues a Stop Grant Acknowledge special transaction and stops
providing internal clock signals to all units except the bus and APIC units. The processor
continues to snoop bus transactions and service interrupts while in the Stop Grant state. When
STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution.
The assertion of STPCLK# has no affect on the bus clock.
TCK (I - 1.5V Tolerant)
The TCK (Test Clock) signal provides the clock input for the test bus (also known as the test
access port).
TDI (I - 1.5V Tolerant)
The TDI (Test Data In) signal transfers serial test data to the processor. TDI provides the serial
input needed for JTAG support.
TDO (O - 1.5V Tolerant Open-drain)
The TDO (Test Data Out) signal transfers serial test data from the processor. TDO provides the
serial output needed for JTAG support.
TESTHI (I - 1.5V Tolerant)
The TESTHI (Test input High) is used during processor test and needs to be pulled high during
normal operation.
TESTLO[2:1] (I - 1.5V Tolerant)
The TESTLO[2:1] (Test input Low) signals are used during processor test and needs to be pulled
to ground during normal operation.
TESTP (Analog)
The TESTP (Test Point) signals are connected to Vcc and Vss at opposite ends of the die. These
signals can be used to monitor the Vcc level on the die. Route the TESTP signals to test points or
leave them unconnected. Do not short the TESTP signals together.
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