
Electrical Specifications
32
Dual-Core Intel Xeon Processor 3000 Series Datasheet
2.7.9
BCLK[1:0] Specifications (CK410 based Platforms)
§
Table 2-19. Front Side Bus Differential BCLK Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Figure
Notes1
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
VL
Input Low Voltage
-0.150
0.000
N/A
V
-
VH
Input High Voltage
0.660
0.700
0.850
V
-
VCROSS(abs)
Absolute Crossing
Point
0.250
N/A
0.550
V
2, 3
2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of BCLK1.
3. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
VCROSS(rel)
Relative Crossing Point
0.250 +
0.5(VHavg – 0.700)
N/A
0.550 +
0.5(VHavg – 0.700)
V
4. VHavg is the statistical average of the VH measured by the oscilloscope.
5. VHavg can be measured directly using “Vtop” on Agilent* oscilloscopes and “High” on Tektronix* oscilloscopes.
ΔVCROSS
Range of Crossing
Points
N/A
0.140
V
-
VOS
Overshoot
N/A
VH + 0.3
V
6
6. Overshoot is defined as the absolute value of the maximum voltage.
VUS
Undershoot
-0.300
N/A
V
7
7. Undershoot is defined as the absolute value of the minimum voltage.
VRBM
Ringback Margin
0.200
N/A
V
8
8. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum
Falling Edge Ringback.
VTM
Threshold Region
VCROSS – 0.100
N/A
VCROSS + 0.100
V
9
9. Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches. It
includes input threshold hysteresis.
Figure 2-7. Differential Clock Crosspoint Specification
660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850
200
250
300
350
400
450
500
550
600
650
VHavg (mV)
Cr
os
s
in
g
Poi
n
t
(m
V
)
550 mV
250 mV
250 + 0.5 (VHavg - 700)
550 + 0.5 (VHavg - 700)