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參數(shù)資料
| 型號： | BX80532KE2000D |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 2000 MHz, MICROPROCESSOR, XMA |
| 文件頁數(shù)： | 67/102頁 |
| 文件大?。?/td> | 1464K |
| 代理商： | BX80532KE2000D |
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Intel Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz
67
SMI#
I
SMI# (System Management Interrupt) is asserted asynchronously by system logic.
On accepting a System Management Interrupt, processors save the current state
and enter System Management Mode (SMM). An SMI Acknowledge transaction is
issued, and the processor begins program execution from the SMM handler.
If SMI# is asserted during the deassertion of RESET# the processor will tri-state its
outputs.
3
STPCLK#
I
STPCLK# (Stop Clock), when asserted, causes processors to enter a low power
Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and
stops providing internal clock signals to all processor core units except the front
side bus and APIC units. The processor continues to snoop bus transactions and
service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the
processor restarts its internal clock to all units and resumes execution. The
assertion of STPCLK# has no effect on the bus clock; STPCLK# is an
asynchronous input.
3
TCK
I
TCK (Test Clock) provides the clock input for the processor Test Bus (also known
as the Test Access Port).
TDI
I
TDI (Test Data In) transfers serial test data into the processor. TDI provides the
serial input needed for JTAG specification support.
TDO
O
TDO (Test Data Out) transfers serial test data out of the processor. TDO provides
the serial output needed for JTAG specification support.
TESTHI[6:0]
I
All TESTHI[6:0] pins should be individually connected to VCC via a pull-up resistor
which matches the trace impedance within a range of ±10 ohms. TESTHI[3:0] and
TESTHI[6:5] may all be tied together and pulled up to VCC with a single resistor if
desired. However, utilization of boundary scan test will not be functional if these
pins are connected together. TESTHI4 must always be pulled up independently
from the other TESTHI pins. For optimum noise margin, all pull-up resistor values
used for TESTHI[6:0] pins should have a resistance value within ±20 percent of the
impedance of the baseboard transmission line traces. For example, if the trace
impedance is 50
, then a value between 40 and 60 should be used. The
TESTHI[6:0] termination recommendations provided in the Intel XeonTM
processor datasheet are still suitable for the Intel XeonTM processor with 533 MHz
Front Side Bus. However, Intel recommends new designs or designs undergoing
design updates follow the trace impedance matching termination guidelines given
in this section.
THERMTRIP#
O
Activation of THERMTRIP# (Thermal Trip) indicates the processor junction
temperature has reached a level beyond which permanent silicon damage may
occur. Measurement of the temperature is accomplished through an internal
thermal sensor which is configured to trip at approximately 135 °C. To properly
protect the processor, power must be removed upon THERMTRIP# becoming
active. See Figure 6 for the appropriate power down sequence and timing
requirement. In parallel, the processor will attempt to reduce its temperature by
shutting off internal clocks and stopping all program execution. Once activated,
THERMTRIP# remains latched and the processor will be stopped until RESET# is
asserted. A RESET# pulse will reset the processor and execution will begin at the
boot vector. If the temperature has not dropped below the trip level, the processor
will assert THERMTRIP# and return to the shutdown state. The processor releases
THERMTRIP# when RESET# is activated even if the processor is still too hot.
This signal do not have on-die termination and must be terminated at the end
agent. See the appropriate platform design guidelines for additional
information
.
2
THERMDA
O
Thermal Diode Anode.
THERMDC
O
Thermal Diode Cathode.
Table 41. Signal Definitions (Sheet 8 of 9)
Name
Type
Description
Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BX80532KC1900E | 1900 MHz, MICROPROCESSOR |
| BU-61582D0-290S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61582D0-300K | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61582D1-391Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61582D1-410S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BX80532KE2000DU | 制造商:Intel 功能描述:XEON 2.0GHZ 533FSB 1U - Boxed Product (Development Kits) |
| BX80532KE2400DSL73L | 制造商:Intel 功能描述: |
| BX80532KE2400E | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.4GHZ - Boxed Product (Development Kits) |
| BX80532KE2400EU | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.4GHZ - Boxed Product (Development Kits) |
| BX80532KE2667D | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.66GHZ - Boxed Product (Development Kits) |
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